IOMMU Fixes for Linux v5.3-rc1
Including: - Revert an Intel VT-d patch that caused boot problems on some machines - Fix AMD IOMMU interrupts with x2apic enabled - Fix a potential crash when Intel VT-d domain allocation fails - Fix crash in Intel VT-d driver when accessing a domain without a flush queue - Formatting fix for new Intel VT-d debugfs code - Fix for use-after-free bug in IOVA code - Fix for a NULL-pointer dereference in Intel VT-d driver when PCI hotplug is used - Compilation fix for one of the previous fixes -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAl06xUwACgkQK/BELZcB GuMsZQ/6Ap+3USes8+Fru1IwGCpBegPlHtl64/WGDdd3JJ5bF3upuPSMulr1U6sa GHWAHa6ZKwXbEe3NzVqo5jGTK6E6TocrGaVmxN+3Ncu/KMcJyew3bmJMw8xvbpF/ VA4vGH7DbEaXOHXHIdCPbE5zOetB/AxoEeUbd45K3ZCvypEz7bTd6E0w9bXmBlml o+z77fRedi4C4srrjsPHgm8JwZYz/QvIRZp+Jr7XhRB/NkbC4ny6jrg+gNWqiqD8 PouSHRw8g2TKzIrLH7syodYCwY+e4ZzCAUVjnyFihq/+qUxK4D3AiFBQeY/nkmd6 wPtfTiKgY0My9z4sPjFRRanPIw3Su77ki1q61+MAZwI6ZGDRla7EP+NQw9h6fFp5 Jdk4fStZA//Nr8zESpVnlYsbS31prJYPKxfroksS6skDB49mmGkPq2jPvrLFJbgz +qqCfpoICTSuUKPduCDVGY1oKkNP5n+pZ9cgPxO3LWwlHhtLAwlo4PjNNLfBLeSC bP7yswgeq/CYywaIAU6tDFfA0AoEnj4q1/v8K93T8zEWu23e3XJQp864DncJPZHc cxcsX3Q2DdASses1GKn/PRRBMdHMv+yRa8evKPwc7q7K2xuTXuHCXL62kCewbbgD ph5MSdv0vSHUBSdRnmvk0LL1FBRc3DkQMCnb/z0xxlM22sQs2v0= =F+hM -----END PGP SIGNATURE----- Merge tag 'iommu-fixes-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull IOMMU fixes from Joerg Roedel: - revert an Intel VT-d patch that caused boot problems on some machines - fix AMD IOMMU interrupts with x2apic enabled - fix a potential crash when Intel VT-d domain allocation fails - fix crash in Intel VT-d driver when accessing a domain without a flush queue - formatting fix for new Intel VT-d debugfs code - fix for use-after-free bug in IOVA code - fix for a NULL-pointer dereference in Intel VT-d driver when PCI hotplug is used - compilation fix for one of the previous fixes * tag 'iommu-fixes-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/amd: Add support for X2APIC IOMMU interrupts iommu/iova: Fix compilation error with !CONFIG_IOMMU_IOVA iommu/vt-d: Print pasid table entries MSB to LSB in debugfs iommu/iova: Remove stale cached32_node iommu/vt-d: Check if domain->pgd was allocated iommu/vt-d: Don't queue_iova() if there is no flush queue iommu/vt-d: Avoid duplicated pci dma alias consideration Revert "iommu/vt-d: Consolidate domain_init() to avoid duplication"alistair/sunxi64-5.4-dsi
Linus Torvalds
commit
b381c016c5
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@ -23,6 +23,8 @@
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#include <linux/mem_encrypt.h>
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#include <asm/pci-direct.h>
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#include <asm/iommu.h>
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#include <asm/apic.h>
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#include <asm/msidef.h>
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#include <asm/gart.h>
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#include <asm/x86_init.h>
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#include <asm/iommu_table.h>
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@ -1920,6 +1922,90 @@ static int iommu_setup_msi(struct amd_iommu *iommu)
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return 0;
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}
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#define XT_INT_DEST_MODE(x) (((x) & 0x1ULL) << 2)
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#define XT_INT_DEST_LO(x) (((x) & 0xFFFFFFULL) << 8)
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#define XT_INT_VEC(x) (((x) & 0xFFULL) << 32)
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#define XT_INT_DEST_HI(x) ((((x) >> 24) & 0xFFULL) << 56)
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/**
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* Setup the IntCapXT registers with interrupt routing information
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* based on the PCI MSI capability block registers, accessed via
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* MMIO MSI address low/hi and MSI data registers.
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*/
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static void iommu_update_intcapxt(struct amd_iommu *iommu)
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{
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u64 val;
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u32 addr_lo = readl(iommu->mmio_base + MMIO_MSI_ADDR_LO_OFFSET);
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u32 addr_hi = readl(iommu->mmio_base + MMIO_MSI_ADDR_HI_OFFSET);
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u32 data = readl(iommu->mmio_base + MMIO_MSI_DATA_OFFSET);
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bool dm = (addr_lo >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
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u32 dest = ((addr_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xFF);
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if (x2apic_enabled())
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dest |= MSI_ADDR_EXT_DEST_ID(addr_hi);
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val = XT_INT_VEC(data & 0xFF) |
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XT_INT_DEST_MODE(dm) |
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XT_INT_DEST_LO(dest) |
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XT_INT_DEST_HI(dest);
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/**
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* Current IOMMU implemtation uses the same IRQ for all
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* 3 IOMMU interrupts.
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*/
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writeq(val, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET);
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writeq(val, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET);
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writeq(val, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET);
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}
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static void _irq_notifier_notify(struct irq_affinity_notify *notify,
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const cpumask_t *mask)
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{
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struct amd_iommu *iommu;
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for_each_iommu(iommu) {
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if (iommu->dev->irq == notify->irq) {
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iommu_update_intcapxt(iommu);
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break;
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}
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}
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}
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static void _irq_notifier_release(struct kref *ref)
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{
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}
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static int iommu_init_intcapxt(struct amd_iommu *iommu)
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{
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int ret;
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struct irq_affinity_notify *notify = &iommu->intcapxt_notify;
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/**
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* IntCapXT requires XTSup=1, which can be inferred
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* amd_iommu_xt_mode.
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*/
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if (amd_iommu_xt_mode != IRQ_REMAP_X2APIC_MODE)
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return 0;
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/**
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* Also, we need to setup notifier to update the IntCapXT registers
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* whenever the irq affinity is changed from user-space.
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*/
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notify->irq = iommu->dev->irq;
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notify->notify = _irq_notifier_notify,
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notify->release = _irq_notifier_release,
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ret = irq_set_affinity_notifier(iommu->dev->irq, notify);
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if (ret) {
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pr_err("Failed to register irq affinity notifier (devid=%#x, irq %d)\n",
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iommu->devid, iommu->dev->irq);
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return ret;
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}
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iommu_update_intcapxt(iommu);
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iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN);
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return ret;
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}
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static int iommu_init_msi(struct amd_iommu *iommu)
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{
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int ret;
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@ -1936,6 +2022,10 @@ static int iommu_init_msi(struct amd_iommu *iommu)
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return ret;
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enable_faults:
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ret = iommu_init_intcapxt(iommu);
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if (ret)
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return ret;
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iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
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if (iommu->ppr_log != NULL)
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@ -60,6 +60,12 @@
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#define MMIO_PPR_LOG_OFFSET 0x0038
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#define MMIO_GA_LOG_BASE_OFFSET 0x00e0
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#define MMIO_GA_LOG_TAIL_OFFSET 0x00e8
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#define MMIO_MSI_ADDR_LO_OFFSET 0x015C
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#define MMIO_MSI_ADDR_HI_OFFSET 0x0160
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#define MMIO_MSI_DATA_OFFSET 0x0164
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#define MMIO_INTCAPXT_EVT_OFFSET 0x0170
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#define MMIO_INTCAPXT_PPR_OFFSET 0x0178
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#define MMIO_INTCAPXT_GALOG_OFFSET 0x0180
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#define MMIO_CMD_HEAD_OFFSET 0x2000
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#define MMIO_CMD_TAIL_OFFSET 0x2008
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#define MMIO_EVT_HEAD_OFFSET 0x2010
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@ -150,6 +156,7 @@
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#define CONTROL_GALOG_EN 0x1CULL
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#define CONTROL_GAINT_EN 0x1DULL
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#define CONTROL_XT_EN 0x32ULL
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#define CONTROL_INTCAPXT_EN 0x33ULL
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#define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
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#define CTRL_INV_TO_NONE 0
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@ -592,6 +599,8 @@ struct amd_iommu {
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/* DebugFS Info */
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struct dentry *debugfs;
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#endif
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/* IRQ notifier for IntCapXT interrupt */
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struct irq_affinity_notify intcapxt_notify;
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};
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static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev)
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@ -162,9 +162,9 @@ static inline void print_tbl_walk(struct seq_file *m)
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(u64)0, (u64)0, (u64)0);
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else
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seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n",
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tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[0],
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tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2],
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tbl_wlk->pasid_tbl_entry->val[1],
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tbl_wlk->pasid_tbl_entry->val[2]);
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tbl_wlk->pasid_tbl_entry->val[0]);
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}
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static void pasid_tbl_walk(struct seq_file *m, struct pasid_entry *tbl_entry,
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@ -339,8 +339,6 @@ static void domain_exit(struct dmar_domain *domain);
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static void domain_remove_dev_info(struct dmar_domain *domain);
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static void dmar_remove_one_dev_info(struct device *dev);
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static void __dmar_remove_one_dev_info(struct device_domain_info *info);
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static void domain_context_clear(struct intel_iommu *iommu,
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struct device *dev);
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static int domain_detach_iommu(struct dmar_domain *domain,
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struct intel_iommu *iommu);
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static bool device_is_rmrr_locked(struct device *dev);
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@ -1833,9 +1831,65 @@ static inline int guestwidth_to_adjustwidth(int gaw)
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return agaw;
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}
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static int domain_init(struct dmar_domain *domain, struct intel_iommu *iommu,
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int guest_width)
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{
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int adjust_width, agaw;
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unsigned long sagaw;
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int err;
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init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN);
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err = init_iova_flush_queue(&domain->iovad,
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iommu_flush_iova, iova_entry_free);
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if (err)
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return err;
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domain_reserve_special_ranges(domain);
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/* calculate AGAW */
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if (guest_width > cap_mgaw(iommu->cap))
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guest_width = cap_mgaw(iommu->cap);
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domain->gaw = guest_width;
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adjust_width = guestwidth_to_adjustwidth(guest_width);
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agaw = width_to_agaw(adjust_width);
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sagaw = cap_sagaw(iommu->cap);
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if (!test_bit(agaw, &sagaw)) {
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/* hardware doesn't support it, choose a bigger one */
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pr_debug("Hardware doesn't support agaw %d\n", agaw);
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agaw = find_next_bit(&sagaw, 5, agaw);
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if (agaw >= 5)
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return -ENODEV;
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}
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domain->agaw = agaw;
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if (ecap_coherent(iommu->ecap))
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domain->iommu_coherency = 1;
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else
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domain->iommu_coherency = 0;
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if (ecap_sc_support(iommu->ecap))
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domain->iommu_snooping = 1;
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else
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domain->iommu_snooping = 0;
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if (intel_iommu_superpage)
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domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
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else
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domain->iommu_superpage = 0;
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domain->nid = iommu->node;
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/* always allocate the top pgd */
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domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
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if (!domain->pgd)
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return -ENOMEM;
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__iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
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return 0;
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}
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static void domain_exit(struct dmar_domain *domain)
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{
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struct page *freelist;
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/* Remove associated devices and clear attached or cached domains */
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domain_remove_dev_info(domain);
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@ -1843,9 +1897,12 @@ static void domain_exit(struct dmar_domain *domain)
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/* destroy iovas */
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put_iova_domain(&domain->iovad);
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freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
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if (domain->pgd) {
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struct page *freelist;
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dma_free_pagelist(freelist);
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freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
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dma_free_pagelist(freelist);
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}
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free_domain_mem(domain);
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}
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@ -2048,26 +2105,9 @@ out_unlock:
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return ret;
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}
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struct domain_context_mapping_data {
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struct dmar_domain *domain;
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struct intel_iommu *iommu;
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struct pasid_table *table;
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};
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static int domain_context_mapping_cb(struct pci_dev *pdev,
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u16 alias, void *opaque)
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{
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struct domain_context_mapping_data *data = opaque;
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return domain_context_mapping_one(data->domain, data->iommu,
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data->table, PCI_BUS_NUM(alias),
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alias & 0xff);
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}
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static int
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domain_context_mapping(struct dmar_domain *domain, struct device *dev)
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{
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struct domain_context_mapping_data data;
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struct pasid_table *table;
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struct intel_iommu *iommu;
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u8 bus, devfn;
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@ -2077,17 +2117,7 @@ domain_context_mapping(struct dmar_domain *domain, struct device *dev)
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return -ENODEV;
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table = intel_pasid_get_table(dev);
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if (!dev_is_pci(dev))
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return domain_context_mapping_one(domain, iommu, table,
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bus, devfn);
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data.domain = domain;
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data.iommu = iommu;
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data.table = table;
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return pci_for_each_dma_alias(to_pci_dev(dev),
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&domain_context_mapping_cb, &data);
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return domain_context_mapping_one(domain, iommu, table, bus, devfn);
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}
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static int domain_context_mapped_cb(struct pci_dev *pdev,
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@ -2513,31 +2543,6 @@ static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque)
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return 0;
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}
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static int domain_init(struct dmar_domain *domain, int guest_width)
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{
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int adjust_width;
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init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN);
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domain_reserve_special_ranges(domain);
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/* calculate AGAW */
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domain->gaw = guest_width;
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adjust_width = guestwidth_to_adjustwidth(guest_width);
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domain->agaw = width_to_agaw(adjust_width);
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domain->iommu_coherency = 0;
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domain->iommu_snooping = 0;
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domain->iommu_superpage = 0;
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domain->max_addr = 0;
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/* always allocate the top pgd */
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domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
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if (!domain->pgd)
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return -ENOMEM;
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domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
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return 0;
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}
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static struct dmar_domain *find_or_alloc_domain(struct device *dev, int gaw)
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{
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struct device_domain_info *info;
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@ -2575,19 +2580,11 @@ static struct dmar_domain *find_or_alloc_domain(struct device *dev, int gaw)
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domain = alloc_domain(0);
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if (!domain)
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return NULL;
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if (domain_init(domain, gaw)) {
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if (domain_init(domain, iommu, gaw)) {
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domain_exit(domain);
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return NULL;
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}
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if (init_iova_flush_queue(&domain->iovad,
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iommu_flush_iova,
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iova_entry_free)) {
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pr_warn("iova flush queue initialization failed\n");
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intel_iommu_strict = 1;
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}
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out:
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return domain;
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}
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@ -2692,6 +2689,8 @@ static int domain_prepare_identity_map(struct device *dev,
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return iommu_domain_identity_map(domain, start, end);
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}
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static int md_domain_init(struct dmar_domain *domain, int guest_width);
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static int __init si_domain_init(int hw)
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{
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struct dmar_rmrr_unit *rmrr;
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|
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@ -2702,7 +2701,7 @@ static int __init si_domain_init(int hw)
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if (!si_domain)
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return -EFAULT;
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if (domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
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if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
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domain_exit(si_domain);
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return -EFAULT;
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}
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|
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@ -3564,7 +3563,8 @@ static void intel_unmap(struct device *dev, dma_addr_t dev_addr, size_t size)
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freelist = domain_unmap(domain, start_pfn, last_pfn);
|
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if (intel_iommu_strict || (pdev && pdev->untrusted)) {
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if (intel_iommu_strict || (pdev && pdev->untrusted) ||
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!has_iova_flush_queue(&domain->iovad)) {
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iommu_flush_iotlb_psi(iommu, domain, start_pfn,
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nrpages, !freelist, 0);
|
||||
/* free iova */
|
||||
|
|
@ -4758,28 +4758,6 @@ out_free_dmar:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int domain_context_clear_one_cb(struct pci_dev *pdev, u16 alias, void *opaque)
|
||||
{
|
||||
struct intel_iommu *iommu = opaque;
|
||||
|
||||
domain_context_clear_one(iommu, PCI_BUS_NUM(alias), alias & 0xff);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* NB - intel-iommu lacks any sort of reference counting for the users of
|
||||
* dependent devices. If multiple endpoints have intersecting dependent
|
||||
* devices, unbinding the driver from any one of them will possibly leave
|
||||
* the others unable to operate.
|
||||
*/
|
||||
static void domain_context_clear(struct intel_iommu *iommu, struct device *dev)
|
||||
{
|
||||
if (!iommu || !dev || !dev_is_pci(dev))
|
||||
return;
|
||||
|
||||
pci_for_each_dma_alias(to_pci_dev(dev), &domain_context_clear_one_cb, iommu);
|
||||
}
|
||||
|
||||
static void __dmar_remove_one_dev_info(struct device_domain_info *info)
|
||||
{
|
||||
struct dmar_domain *domain;
|
||||
|
|
@ -4800,7 +4778,7 @@ static void __dmar_remove_one_dev_info(struct device_domain_info *info)
|
|||
PASID_RID2PASID);
|
||||
|
||||
iommu_disable_dev_iotlb(info);
|
||||
domain_context_clear(iommu, info->dev);
|
||||
domain_context_clear_one(iommu, info->bus, info->devfn);
|
||||
intel_pasid_free_table(info->dev);
|
||||
}
|
||||
|
||||
|
|
@ -4829,6 +4807,31 @@ static void dmar_remove_one_dev_info(struct device *dev)
|
|||
spin_unlock_irqrestore(&device_domain_lock, flags);
|
||||
}
|
||||
|
||||
static int md_domain_init(struct dmar_domain *domain, int guest_width)
|
||||
{
|
||||
int adjust_width;
|
||||
|
||||
init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN);
|
||||
domain_reserve_special_ranges(domain);
|
||||
|
||||
/* calculate AGAW */
|
||||
domain->gaw = guest_width;
|
||||
adjust_width = guestwidth_to_adjustwidth(guest_width);
|
||||
domain->agaw = width_to_agaw(adjust_width);
|
||||
|
||||
domain->iommu_coherency = 0;
|
||||
domain->iommu_snooping = 0;
|
||||
domain->iommu_superpage = 0;
|
||||
domain->max_addr = 0;
|
||||
|
||||
/* always allocate the top pgd */
|
||||
domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
|
||||
if (!domain->pgd)
|
||||
return -ENOMEM;
|
||||
domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct iommu_domain *intel_iommu_domain_alloc(unsigned type)
|
||||
{
|
||||
struct dmar_domain *dmar_domain;
|
||||
|
|
@ -4843,7 +4846,7 @@ static struct iommu_domain *intel_iommu_domain_alloc(unsigned type)
|
|||
pr_err("Can't allocate dmar_domain\n");
|
||||
return NULL;
|
||||
}
|
||||
if (domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
|
||||
if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
|
||||
pr_err("Domain initialization failed\n");
|
||||
domain_exit(dmar_domain);
|
||||
return NULL;
|
||||
|
|
|
|||
|
|
@ -54,9 +54,14 @@ init_iova_domain(struct iova_domain *iovad, unsigned long granule,
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(init_iova_domain);
|
||||
|
||||
bool has_iova_flush_queue(struct iova_domain *iovad)
|
||||
{
|
||||
return !!iovad->fq;
|
||||
}
|
||||
|
||||
static void free_iova_flush_queue(struct iova_domain *iovad)
|
||||
{
|
||||
if (!iovad->fq)
|
||||
if (!has_iova_flush_queue(iovad))
|
||||
return;
|
||||
|
||||
if (timer_pending(&iovad->fq_timer))
|
||||
|
|
@ -74,13 +79,14 @@ static void free_iova_flush_queue(struct iova_domain *iovad)
|
|||
int init_iova_flush_queue(struct iova_domain *iovad,
|
||||
iova_flush_cb flush_cb, iova_entry_dtor entry_dtor)
|
||||
{
|
||||
struct iova_fq __percpu *queue;
|
||||
int cpu;
|
||||
|
||||
atomic64_set(&iovad->fq_flush_start_cnt, 0);
|
||||
atomic64_set(&iovad->fq_flush_finish_cnt, 0);
|
||||
|
||||
iovad->fq = alloc_percpu(struct iova_fq);
|
||||
if (!iovad->fq)
|
||||
queue = alloc_percpu(struct iova_fq);
|
||||
if (!queue)
|
||||
return -ENOMEM;
|
||||
|
||||
iovad->flush_cb = flush_cb;
|
||||
|
|
@ -89,13 +95,17 @@ int init_iova_flush_queue(struct iova_domain *iovad,
|
|||
for_each_possible_cpu(cpu) {
|
||||
struct iova_fq *fq;
|
||||
|
||||
fq = per_cpu_ptr(iovad->fq, cpu);
|
||||
fq = per_cpu_ptr(queue, cpu);
|
||||
fq->head = 0;
|
||||
fq->tail = 0;
|
||||
|
||||
spin_lock_init(&fq->lock);
|
||||
}
|
||||
|
||||
smp_wmb();
|
||||
|
||||
iovad->fq = queue;
|
||||
|
||||
timer_setup(&iovad->fq_timer, fq_flush_timeout, 0);
|
||||
atomic_set(&iovad->fq_timer_on, 0);
|
||||
|
||||
|
|
@ -127,8 +137,9 @@ __cached_rbnode_delete_update(struct iova_domain *iovad, struct iova *free)
|
|||
struct iova *cached_iova;
|
||||
|
||||
cached_iova = rb_entry(iovad->cached32_node, struct iova, node);
|
||||
if (free->pfn_hi < iovad->dma_32bit_pfn &&
|
||||
free->pfn_lo >= cached_iova->pfn_lo) {
|
||||
if (free == cached_iova ||
|
||||
(free->pfn_hi < iovad->dma_32bit_pfn &&
|
||||
free->pfn_lo >= cached_iova->pfn_lo)) {
|
||||
iovad->cached32_node = rb_next(&free->node);
|
||||
iovad->max32_alloc_size = iovad->dma_32bit_pfn;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -155,6 +155,7 @@ struct iova *reserve_iova(struct iova_domain *iovad, unsigned long pfn_lo,
|
|||
void copy_reserved_iova(struct iova_domain *from, struct iova_domain *to);
|
||||
void init_iova_domain(struct iova_domain *iovad, unsigned long granule,
|
||||
unsigned long start_pfn);
|
||||
bool has_iova_flush_queue(struct iova_domain *iovad);
|
||||
int init_iova_flush_queue(struct iova_domain *iovad,
|
||||
iova_flush_cb flush_cb, iova_entry_dtor entry_dtor);
|
||||
struct iova *find_iova(struct iova_domain *iovad, unsigned long pfn);
|
||||
|
|
@ -235,6 +236,11 @@ static inline void init_iova_domain(struct iova_domain *iovad,
|
|||
{
|
||||
}
|
||||
|
||||
static inline bool has_iova_flush_queue(struct iova_domain *iovad)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline int init_iova_flush_queue(struct iova_domain *iovad,
|
||||
iova_flush_cb flush_cb,
|
||||
iova_entry_dtor entry_dtor)
|
||||
|
|
|
|||
Loading…
Reference in New Issue