ARC fixes for 4.4-rc1
- A bunch of brown paper bag bugs (MAINTAINERS list email, SMP build failure)
- cpu_relax() now compiler barrier for UP as well
- Handling of userspace Bus Errors for ARCompact builds
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Merge tag 'arc-4.4-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
"Found a couple of brown paper bag bugs with the prev pull request
(including a SMP build breakage report from Guenter). Since these are
urgent I also decided to send over a bunch of other pending fixes
which could have otherwise waited an rc or two.
Summary:
- A bunch of brown paper bag bugs (MAINTAINERS list email, SMP build
failure)
- cpu_relax() now compiler barrier for UP as well
- handling of userspace Bus Errors for ARCompact builds"
* tag 'arc-4.4-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: Fix silly typo in MAINTAINERS file
ARC: cpu_relax() to be compiler barrier even for UP
ARC: use ASL assembler mnemonic
ARC: [arcompact] Handle bus error from userspace as Interrupt not exception
ARC: remove extraneous header include
ARCv2: lib: memcpy: use local symbols
hifive-unleashed-5.1
Linus Torvalds
commit
b3a0d9a232
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@ -10300,7 +10300,7 @@ F: include/net/switchdev.h
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SYNOPSYS ARC ARCHITECTURE
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M: Vineet Gupta <vgupta@synopsys.com>
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L: linux-snps-arc@lists.infraded.org
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L: linux-snps-arc@lists.infradead.org
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S: Supported
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F: arch/arc/
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F: Documentation/devicetree/bindings/arc/*
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@ -57,11 +57,7 @@ struct task_struct;
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* A lot of busy-wait loops in SMP are based off of non-volatile data otherwise
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* get optimised away by gcc
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*/
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#ifdef CONFIG_SMP
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#define cpu_relax() __asm__ __volatile__ ("" : : : "memory")
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#else
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#define cpu_relax() do { } while (0)
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#endif
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#define cpu_relax_lowlatency() cpu_relax()
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@ -91,6 +91,25 @@ ENTRY(EV_DCError)
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flag 1
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END(EV_DCError)
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; ---------------------------------------------
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; Memory Error Exception Handler
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; - Unlike ARCompact, handles Bus errors for both User/Kernel mode,
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; Instruction fetch or Data access, under a single Exception Vector
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; ---------------------------------------------
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ENTRY(mem_service)
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EXCEPTION_PROLOGUE
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lr r0, [efa]
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mov r1, sp
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FAKE_RET_FROM_EXCPN
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bl do_memory_error
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b ret_from_exception
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END(mem_service)
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ENTRY(EV_Misaligned)
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EXCEPTION_PROLOGUE
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@ -142,16 +142,12 @@ int1_saved_reg:
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.zero 4
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/* Each Interrupt level needs its own scratch */
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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ARCFP_DATA int2_saved_reg
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.type int2_saved_reg, @object
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.size int2_saved_reg, 4
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int2_saved_reg:
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.zero 4
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#endif
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; ---------------------------------------------
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.section .text, "ax",@progbits
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@ -215,6 +211,31 @@ END(handle_interrupt_level2)
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#endif
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; ---------------------------------------------
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; User Mode Memory Bus Error Interrupt Handler
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; (Kernel mode memory errors handled via seperate exception vectors)
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; ---------------------------------------------
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ENTRY(mem_service)
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INTERRUPT_PROLOGUE 2
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mov r0, ilink2
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mov r1, sp
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; User process needs to be killed with SIGBUS, but first need to get
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; out of the L2 interrupt context (drop to pure kernel mode) and jump
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; off to "C" code where SIGBUS in enqueued
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lr r3, [status32]
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bclr r3, r3, STATUS_A2_BIT
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or r3, r3, (STATUS_E1_MASK|STATUS_E2_MASK)
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sr r3, [status32_l2]
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mov ilink2, 1f
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rtie
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1:
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bl do_memory_error
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b ret_from_exception
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END(mem_service)
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; ---------------------------------------------
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; Level 1 ISR
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; ---------------------------------------------
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@ -92,23 +92,6 @@ ENTRY(instr_service)
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b ret_from_exception
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END(instr_service)
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; ---------------------------------------------
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; Memory Error Exception Handler
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; ---------------------------------------------
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ENTRY(mem_service)
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EXCEPTION_PROLOGUE
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lr r0, [efa]
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mov r1, sp
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FAKE_RET_FROM_EXCPN
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bl do_memory_error
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b ret_from_exception
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END(mem_service)
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; ---------------------------------------------
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; Machine Check Exception Handler
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; ---------------------------------------------
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@ -50,26 +50,26 @@ ENTRY(memcpy)
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;;; if size <= 8
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cmp r2, 8
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bls.d @smallchunk
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bls.d @.Lsmallchunk
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mov.f lp_count, r2
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and.f r4, r0, 0x03
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rsub lp_count, r4, 4
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lpnz @aligndestination
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lpnz @.Laligndestination
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;; LOOP BEGIN
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ldb.ab r5, [r1,1]
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sub r2, r2, 1
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stb.ab r5, [r3,1]
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aligndestination:
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.Laligndestination:
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;;; Check the alignment of the source
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and.f r4, r1, 0x03
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bnz.d @sourceunaligned
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bnz.d @.Lsourceunaligned
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;;; CASE 0: Both source and destination are 32bit aligned
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;;; Convert len to Dwords, unfold x4
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lsr.f lp_count, r2, ZOLSHFT
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lpnz @copy32_64bytes
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lpnz @.Lcopy32_64bytes
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;; LOOP START
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LOADX (r6, r1)
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PREFETCH_READ (r1)
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@ -81,25 +81,25 @@ aligndestination:
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STOREX (r8, r3)
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STOREX (r10, r3)
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STOREX (r4, r3)
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copy32_64bytes:
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.Lcopy32_64bytes:
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and.f lp_count, r2, ZOLAND ;Last remaining 31 bytes
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smallchunk:
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lpnz @copyremainingbytes
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.Lsmallchunk:
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lpnz @.Lcopyremainingbytes
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;; LOOP START
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ldb.ab r5, [r1,1]
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stb.ab r5, [r3,1]
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copyremainingbytes:
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.Lcopyremainingbytes:
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j [blink]
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;;; END CASE 0
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sourceunaligned:
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.Lsourceunaligned:
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cmp r4, 2
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beq.d @unalignedOffby2
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beq.d @.LunalignedOffby2
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sub r2, r2, 1
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bhi.d @unalignedOffby3
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bhi.d @.LunalignedOffby3
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ldb.ab r5, [r1, 1]
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;;; CASE 1: The source is unaligned, off by 1
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@ -114,7 +114,7 @@ sourceunaligned:
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or r5, r5, r6
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;; Both src and dst are aligned
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lpnz @copy8bytes_1
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lpnz @.Lcopy8bytes_1
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;; LOOP START
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ld.ab r6, [r1, 4]
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prefetch [r1, 28] ;Prefetch the next read location
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@ -131,7 +131,7 @@ sourceunaligned:
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st.ab r7, [r3, 4]
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st.ab r9, [r3, 4]
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copy8bytes_1:
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.Lcopy8bytes_1:
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;; Write back the remaining 16bits
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EXTRACT_1 (r6, r5, 16)
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@ -141,14 +141,14 @@ copy8bytes_1:
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stb.ab r5, [r3, 1]
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and.f lp_count, r2, 0x07 ;Last 8bytes
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lpnz @copybytewise_1
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lpnz @.Lcopybytewise_1
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;; LOOP START
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ldb.ab r6, [r1,1]
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stb.ab r6, [r3,1]
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copybytewise_1:
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.Lcopybytewise_1:
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j [blink]
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unalignedOffby2:
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.LunalignedOffby2:
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;;; CASE 2: The source is unaligned, off by 2
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ldh.ab r5, [r1, 2]
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sub r2, r2, 1
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@ -159,7 +159,7 @@ unalignedOffby2:
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#ifdef __BIG_ENDIAN__
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asl.nz r5, r5, 16
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#endif
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lpnz @copy8bytes_2
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lpnz @.Lcopy8bytes_2
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;; LOOP START
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ld.ab r6, [r1, 4]
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prefetch [r1, 28] ;Prefetch the next read location
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@ -176,7 +176,7 @@ unalignedOffby2:
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st.ab r7, [r3, 4]
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st.ab r9, [r3, 4]
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copy8bytes_2:
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.Lcopy8bytes_2:
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#ifdef __BIG_ENDIAN__
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lsr.nz r5, r5, 16
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@ -184,14 +184,14 @@ copy8bytes_2:
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sth.ab r5, [r3, 2]
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and.f lp_count, r2, 0x07 ;Last 8bytes
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lpnz @copybytewise_2
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lpnz @.Lcopybytewise_2
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;; LOOP START
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ldb.ab r6, [r1,1]
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stb.ab r6, [r3,1]
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copybytewise_2:
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.Lcopybytewise_2:
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j [blink]
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unalignedOffby3:
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.LunalignedOffby3:
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;;; CASE 3: The source is unaligned, off by 3
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;;; Hence, I need to read 1byte for achieve the 32bit alignment
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@ -201,7 +201,7 @@ unalignedOffby3:
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#ifdef __BIG_ENDIAN__
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asl.ne r5, r5, 24
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#endif
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lpnz @copy8bytes_3
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lpnz @.Lcopy8bytes_3
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;; LOOP START
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ld.ab r6, [r1, 4]
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prefetch [r1, 28] ;Prefetch the next read location
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@ -218,7 +218,7 @@ unalignedOffby3:
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st.ab r7, [r3, 4]
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st.ab r9, [r3, 4]
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copy8bytes_3:
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.Lcopy8bytes_3:
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#ifdef __BIG_ENDIAN__
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lsr.nz r5, r5, 24
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@ -226,11 +226,11 @@ copy8bytes_3:
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stb.ab r5, [r3, 1]
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and.f lp_count, r2, 0x07 ;Last 8bytes
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lpnz @copybytewise_3
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lpnz @.Lcopybytewise_3
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;; LOOP START
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ldb.ab r6, [r1,1]
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stb.ab r6, [r3,1]
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copybytewise_3:
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.Lcopybytewise_3:
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j [blink]
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END(memcpy)
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@ -88,7 +88,7 @@ ex_saved_reg1:
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#ifdef CONFIG_SMP
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sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with
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GET_CPU_ID r0 ; get to per cpu scratch mem,
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lsl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
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asl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
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add r0, @ex_saved_reg1, r0
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#else
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st r0, [@ex_saved_reg1]
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@ -107,7 +107,7 @@ ex_saved_reg1:
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.macro TLBMISS_RESTORE_REGS
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#ifdef CONFIG_SMP
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GET_CPU_ID r0 ; get to per cpu scratch mem
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lsl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
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asl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
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add r0, @ex_saved_reg1, r0
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ld_s r3, [r0,12]
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ld_s r2, [r0, 8]
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|
|
@ -256,7 +256,7 @@ ex_saved_reg1:
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|||
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.macro CONV_PTE_TO_TLB
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and r3, r0, PTE_BITS_RWX ; r w x
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lsl r2, r3, 3 ; Kr Kw Kx 0 0 0 (GLOBAL, kernel only)
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asl r2, r3, 3 ; Kr Kw Kx 0 0 0 (GLOBAL, kernel only)
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||||
and.f 0, r0, _PAGE_GLOBAL
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||||
or.z r2, r2, r3 ; Kr Kw Kx Ur Uw Ux (!GLOBAL, user page)
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||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,6 @@
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|||
|
||||
#include <linux/init.h>
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||||
#include <asm/mach_desc.h>
|
||||
#include <asm/mcip.h>
|
||||
|
||||
/*----------------------- Machine Descriptions ------------------------------
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue