drm/i915: Adjust DisplayPort clocks to use 96MHz reference
For some reason, the DP clocks were based off a 100MHz reference instead of the standard 96MHz reference. This caused some DP monitors to fail to lock to the signal. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Eric Anholt <eric@anholt.net>
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@ -816,24 +816,21 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
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{
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intel_clock_t clock;
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if (target < 200000) {
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clock.dot = 161670;
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clock.p = 20;
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clock.p1 = 2;
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clock.p2 = 10;
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clock.n = 0x01;
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clock.m = 97;
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clock.m1 = 0x10;
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clock.m2 = 0x05;
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clock.n = 2;
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clock.m1 = 23;
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clock.m2 = 8;
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} else {
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clock.dot = 270000;
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clock.p = 10;
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clock.p1 = 1;
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clock.p2 = 10;
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clock.n = 0x02;
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clock.m = 108;
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clock.m1 = 0x12;
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clock.m2 = 0x06;
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clock.n = 1;
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clock.m1 = 14;
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clock.m2 = 2;
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}
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clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
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clock.p = (clock.p1 * clock.p2);
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clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
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memcpy(best_clock, &clock, sizeof(intel_clock_t));
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return true;
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}
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