CLK: ti: add support for ti divider-clock
This patch adds support for TI divider clock binding, which simply uses the basic clock divider to provide the features needed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>hifive-unleashed-5.1
Tero Kristo
Mike Turquette
parent
975e15487d
commit
b4761198bf
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@ -0,0 +1,114 @@
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Binding for TI divider clock
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Binding status: Unstable - ABI compatibility may be broken in the future
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This binding uses the common clock binding[1]. It assumes a
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register-mapped adjustable clock rate divider that does not gate and has
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only one input clock or parent. By default the value programmed into
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the register is one less than the actual divisor value. E.g:
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register value actual divisor value
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0 1
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1 2
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2 3
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This assumption may be modified by the following optional properties:
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ti,index-starts-at-one - valid divisor values start at 1, not the default
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of 0. E.g:
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register value actual divisor value
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1 1
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2 2
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3 3
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ti,index-power-of-two - valid divisor values are powers of two. E.g:
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register value actual divisor value
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0 1
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1 2
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2 4
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Additionally an array of valid dividers may be supplied like so:
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ti,dividers = <4>, <8>, <0>, <16>;
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Which will map the resulting values to a divisor table by their index:
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register value actual divisor value
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0 4
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1 8
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2 <invalid divisor, skipped>
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3 16
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Any zero value in this array means the corresponding bit-value is invalid
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and must not be used.
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The binding must also provide the register to control the divider and
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unless the divider array is provided, min and max dividers. Optionally
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the number of bits to shift that mask, if necessary. If the shift value
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is missing it is the same as supplying a zero shift.
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This binding can also optionally provide support to the hardware autoidle
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feature, see [2].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
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Required properties:
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- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : link to phandle of parent clock
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- reg : offset for register controlling adjustable divider
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Optional properties:
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- clock-output-names : from common clock binding.
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- ti,dividers : array of integers defining divisors
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- ti,bit-shift : number of bits to shift the divider value, defaults to 0
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- ti,min-div : min divisor for dividing the input clock rate, only
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needed if the first divisor is offset from the default value (1)
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- ti,max-div : max divisor for dividing the input clock rate, only needed
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if ti,dividers is not defined.
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- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
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only valid if ti,dividers is not defined.
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- ti,index-power-of-two : valid divisor programming must be a power of two,
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only valid if ti,dividers is not defined.
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- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
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see [2]
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- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
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see [2]
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- ti,set-rate-parent : clk_set_rate is propagated to parent
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Examples:
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dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_usb_ck>;
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ti,max-div = <127>;
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reg = <0x190>;
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ti,index-starts-at-one;
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};
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aess_fclk: aess_fclk@4a004528 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&abe_clk>;
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ti,bit-shift = <24>;
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reg = <0x528>;
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ti,max-div = <2>;
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};
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dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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reg = <0x0134>;
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ti,index-starts-at-one;
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};
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ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&corex2_fck>;
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ti,bit-shift = <8>;
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reg = <0x0a40>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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};
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@ -1,4 +1,4 @@
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ifneq ($(CONFIG_OF),)
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obj-y += clk.o autoidle.o
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clk-common = dpll.o composite.o
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clk-common = dpll.o composite.o divider.o
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endif
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@ -31,7 +31,7 @@
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static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return clk_divider_ops.recalc_rate(hw, parent_rate);
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return ti_clk_divider_ops.recalc_rate(hw, parent_rate);
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}
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static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate,
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@ -0,0 +1,487 @@
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/*
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* TI Divider Clock
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* Tero Kristo <t-kristo@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clk/ti.h>
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#undef pr_fmt
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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#define div_mask(d) ((1 << ((d)->width)) - 1)
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static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
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{
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unsigned int maxdiv = 0;
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div > maxdiv)
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maxdiv = clkt->div;
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return maxdiv;
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}
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static unsigned int _get_maxdiv(struct clk_divider *divider)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return div_mask(divider);
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return 1 << div_mask(divider);
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if (divider->table)
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return _get_table_maxdiv(divider->table);
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return div_mask(divider) + 1;
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}
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static unsigned int _get_table_div(const struct clk_div_table *table,
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unsigned int val)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->val == val)
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return clkt->div;
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return 0;
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}
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static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return val;
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return 1 << val;
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if (divider->table)
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return _get_table_div(divider->table, val);
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return val + 1;
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}
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static unsigned int _get_table_val(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return clkt->val;
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return 0;
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}
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static unsigned int _get_val(struct clk_divider *divider, u8 div)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return div;
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return __ffs(div);
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if (divider->table)
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return _get_table_val(divider->table, div);
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return div - 1;
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}
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static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int div, val;
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val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift;
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val &= div_mask(divider);
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div = _get_div(divider, val);
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if (!div) {
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WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
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"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
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__clk_get_name(hw->clk));
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return parent_rate;
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}
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return parent_rate / div;
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}
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/*
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* The reverse of DIV_ROUND_UP: The maximum number which
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* divided by m is r
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*/
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#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
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static bool _is_valid_table_div(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return true;
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return false;
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}
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static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
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{
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return is_power_of_2(div);
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if (divider->table)
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return _is_valid_table_div(divider->table, div);
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return true;
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}
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static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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unsigned long *best_parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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int i, bestdiv = 0;
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unsigned long parent_rate, best = 0, now, maxdiv;
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unsigned long parent_rate_saved = *best_parent_rate;
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if (!rate)
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rate = 1;
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maxdiv = _get_maxdiv(divider);
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if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
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parent_rate = *best_parent_rate;
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bestdiv = DIV_ROUND_UP(parent_rate, rate);
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bestdiv = bestdiv == 0 ? 1 : bestdiv;
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bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
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return bestdiv;
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}
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/*
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* The maximum divider we can use without overflowing
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* unsigned long in rate * i below
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*/
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maxdiv = min(ULONG_MAX / rate, maxdiv);
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for (i = 1; i <= maxdiv; i++) {
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if (!_is_valid_div(divider, i))
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continue;
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if (rate * i == parent_rate_saved) {
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/*
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* It's the most ideal case if the requested rate can be
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* divided from parent clock without needing to change
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* parent rate, so return the divider immediately.
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*/
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*best_parent_rate = parent_rate_saved;
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return i;
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}
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parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
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MULT_ROUND_UP(rate, i));
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now = parent_rate / i;
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if (now <= rate && now > best) {
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bestdiv = i;
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best = now;
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*best_parent_rate = parent_rate;
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}
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}
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if (!bestdiv) {
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bestdiv = _get_maxdiv(divider);
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*best_parent_rate =
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__clk_round_rate(__clk_get_parent(hw->clk), 1);
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}
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return bestdiv;
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}
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static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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int div;
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div = ti_clk_divider_bestdiv(hw, rate, prate);
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return *prate / div;
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}
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static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int div, value;
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unsigned long flags = 0;
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u32 val;
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div = parent_rate / rate;
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value = _get_val(divider, div);
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if (value > div_mask(divider))
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value = div_mask(divider);
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if (divider->lock)
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spin_lock_irqsave(divider->lock, flags);
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if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
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val = div_mask(divider) << (divider->shift + 16);
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} else {
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val = ti_clk_ll_ops->clk_readl(divider->reg);
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val &= ~(div_mask(divider) << divider->shift);
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}
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val |= value << divider->shift;
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ti_clk_ll_ops->clk_writel(val, divider->reg);
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if (divider->lock)
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spin_unlock_irqrestore(divider->lock, flags);
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return 0;
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}
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const struct clk_ops ti_clk_divider_ops = {
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.recalc_rate = ti_clk_divider_recalc_rate,
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.round_rate = ti_clk_divider_round_rate,
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.set_rate = ti_clk_divider_set_rate,
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};
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static struct clk *_register_divider(struct device *dev, const char *name,
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const char *parent_name,
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unsigned long flags, void __iomem *reg,
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u8 shift, u8 width, u8 clk_divider_flags,
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const struct clk_div_table *table,
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spinlock_t *lock)
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{
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struct clk_divider *div;
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struct clk *clk;
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struct clk_init_data init;
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if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
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if (width + shift > 16) {
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pr_warn("divider value exceeds LOWORD field\n");
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return ERR_PTR(-EINVAL);
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}
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}
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/* allocate the divider */
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div) {
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pr_err("%s: could not allocate divider clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &ti_clk_divider_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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/* struct clk_divider assignments */
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div->reg = reg;
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div->shift = shift;
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div->width = width;
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div->flags = clk_divider_flags;
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div->lock = lock;
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div->hw.init = &init;
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div->table = table;
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/* register the clock */
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clk = clk_register(dev, &div->hw);
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if (IS_ERR(clk))
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kfree(div);
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return clk;
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}
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static struct clk_div_table
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__init *ti_clk_get_div_table(struct device_node *node)
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{
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struct clk_div_table *table;
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const __be32 *divspec;
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u32 val;
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u32 num_div;
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u32 valid_div;
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int i;
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divspec = of_get_property(node, "ti,dividers", &num_div);
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if (!divspec)
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return NULL;
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num_div /= 4;
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valid_div = 0;
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/* Determine required size for divider table */
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for (i = 0; i < num_div; i++) {
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of_property_read_u32_index(node, "ti,dividers", i, &val);
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if (val)
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valid_div++;
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}
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if (!valid_div) {
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pr_err("no valid dividers for %s table\n", node->name);
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return ERR_PTR(-EINVAL);
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}
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table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
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if (!table)
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return ERR_PTR(-ENOMEM);
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valid_div = 0;
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for (i = 0; i < num_div; i++) {
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of_property_read_u32_index(node, "ti,dividers", i, &val);
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if (val) {
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table[valid_div].div = val;
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table[valid_div].val = i;
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valid_div++;
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}
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||||
}
|
||||
|
||||
return table;
|
||||
}
|
||||
|
||||
static int _get_divider_width(struct device_node *node,
|
||||
const struct clk_div_table *table,
|
||||
u8 flags)
|
||||
{
|
||||
u32 min_div;
|
||||
u32 max_div;
|
||||
u32 val = 0;
|
||||
u32 div;
|
||||
|
||||
if (!table) {
|
||||
/* Clk divider table not provided, determine min/max divs */
|
||||
if (of_property_read_u32(node, "ti,min-div", &min_div))
|
||||
min_div = 1;
|
||||
|
||||
if (of_property_read_u32(node, "ti,max-div", &max_div)) {
|
||||
pr_err("no max-div for %s!\n", node->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Determine bit width for the field */
|
||||
if (flags & CLK_DIVIDER_ONE_BASED)
|
||||
val = 1;
|
||||
|
||||
div = min_div;
|
||||
|
||||
while (div < max_div) {
|
||||
if (flags & CLK_DIVIDER_POWER_OF_TWO)
|
||||
div <<= 1;
|
||||
else
|
||||
div++;
|
||||
val++;
|
||||
}
|
||||
} else {
|
||||
div = 0;
|
||||
|
||||
while (table[div].div) {
|
||||
val = table[div].val;
|
||||
div++;
|
||||
}
|
||||
}
|
||||
|
||||
return fls(val);
|
||||
}
|
||||
|
||||
static int __init ti_clk_divider_populate(struct device_node *node,
|
||||
void __iomem **reg, const struct clk_div_table **table,
|
||||
u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
*reg = ti_clk_get_reg_addr(node, 0);
|
||||
if (!*reg)
|
||||
return -EINVAL;
|
||||
|
||||
if (!of_property_read_u32(node, "ti,bit-shift", &val))
|
||||
*shift = val;
|
||||
else
|
||||
*shift = 0;
|
||||
|
||||
*flags = 0;
|
||||
*div_flags = 0;
|
||||
|
||||
if (of_property_read_bool(node, "ti,index-starts-at-one"))
|
||||
*div_flags |= CLK_DIVIDER_ONE_BASED;
|
||||
|
||||
if (of_property_read_bool(node, "ti,index-power-of-two"))
|
||||
*div_flags |= CLK_DIVIDER_POWER_OF_TWO;
|
||||
|
||||
if (of_property_read_bool(node, "ti,set-rate-parent"))
|
||||
*flags |= CLK_SET_RATE_PARENT;
|
||||
|
||||
*table = ti_clk_get_div_table(node);
|
||||
|
||||
if (IS_ERR(*table))
|
||||
return PTR_ERR(*table);
|
||||
|
||||
*width = _get_divider_width(node, *table, *div_flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* of_ti_divider_clk_setup - Setup function for simple div rate clock
|
||||
* @node: device node for this clock
|
||||
*
|
||||
* Sets up a basic divider clock.
|
||||
*/
|
||||
static void __init of_ti_divider_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk *clk;
|
||||
const char *parent_name;
|
||||
void __iomem *reg;
|
||||
u8 clk_divider_flags = 0;
|
||||
u8 width = 0;
|
||||
u8 shift = 0;
|
||||
const struct clk_div_table *table = NULL;
|
||||
u32 flags = 0;
|
||||
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
|
||||
if (ti_clk_divider_populate(node, ®, &table, &flags,
|
||||
&clk_divider_flags, &width, &shift))
|
||||
goto cleanup;
|
||||
|
||||
clk = _register_divider(NULL, node->name, parent_name, flags, reg,
|
||||
shift, width, clk_divider_flags, table, NULL);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
of_ti_clk_autoidle_setup(node);
|
||||
return;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
kfree(table);
|
||||
}
|
||||
CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
|
||||
|
||||
static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk_divider *div;
|
||||
u32 val;
|
||||
|
||||
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
||||
if (!div)
|
||||
return;
|
||||
|
||||
if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
|
||||
&div->flags, &div->width, &div->shift) < 0)
|
||||
goto cleanup;
|
||||
|
||||
if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
|
||||
return;
|
||||
|
||||
cleanup:
|
||||
kfree(div->table);
|
||||
kfree(div);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
|
||||
of_ti_composite_divider_clk_setup);
|
||||
|
|
@ -223,6 +223,8 @@ struct ti_clk_ll_ops {
|
|||
|
||||
extern struct ti_clk_ll_ops *ti_clk_ll_ops;
|
||||
|
||||
extern const struct clk_ops ti_clk_divider_ops;
|
||||
|
||||
#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
|
||||
|
||||
void omap2_init_clk_hw_omap_clocks(struct clk *clk);
|
||||
|
|
|
|||
Loading…
Reference in New Issue