Merge branch 'fixes-rc5' of git://aeryn.fluff.org.uk/bjdooks/linux
This commit is contained in:
commit
b477dfba38
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@ -588,8 +588,6 @@ static void __init bast_map_io(void)
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s3c_device_nand.dev.platform_data = &bast_nand_info;
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s3c_i2c0_set_platdata(&bast_i2c_info);
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s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
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s3c24xx_init_clocks(0);
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s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
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@ -602,6 +600,7 @@ static void __init bast_init(void)
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sysdev_class_register(&bast_pm_sysclass);
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sysdev_register(&bast_pm_sysdev);
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s3c_i2c0_set_platdata(&bast_i2c_info);
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s3c24xx_fb_set_platdata(&bast_fb_info);
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platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
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@ -114,4 +114,8 @@ extern unsigned int SingleCPDO(struct roundingData *roundData,
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extern unsigned int DoubleCPDO(struct roundingData *roundData,
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const unsigned int opcode, FPREG * rFd);
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/* extneded_cpdo.c */
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extern unsigned int ExtendedCPDO(struct roundingData *roundData,
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const unsigned int opcode, FPREG * rFd);
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#endif
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@ -27,10 +27,6 @@
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#include "fpmodule.inl"
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#include "softfloat.h"
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#ifdef CONFIG_FPE_NWFPE_XP
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extern flag floatx80_is_nan(floatx80);
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#endif
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unsigned int PerformFLT(const unsigned int opcode);
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unsigned int PerformFIX(const unsigned int opcode);
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@ -226,6 +226,8 @@ char floatx80_le_quiet( floatx80, floatx80 );
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char floatx80_lt_quiet( floatx80, floatx80 );
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char floatx80_is_signaling_nan( floatx80 );
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extern flag floatx80_is_nan(floatx80);
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#endif
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static inline flag extractFloat32Sign(float32 a)
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@ -306,8 +306,6 @@ struct clk s3c24xx_uclk = {
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int s3c24xx_register_clock(struct clk *clk)
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{
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clk->owner = THIS_MODULE;
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if (clk->enable == NULL)
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clk->enable = clk_null_enable;
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@ -1235,7 +1235,7 @@ int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *d
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EXPORT_SYMBOL(s3c2410_dma_getposition);
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static struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev)
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static inline struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev)
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{
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return container_of(dev, struct s3c2410_dma_chan, dev);
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}
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@ -57,7 +57,7 @@
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#if 1
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#define gpio_dbg(x...) do { } while(0)
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#else
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#define gpio_dbg(x...) printk(KERN_DEBUG ## x)
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#define gpio_dbg(x...) printk(KERN_DEBUG x)
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#endif
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/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where
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@ -61,14 +61,14 @@
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#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28)
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#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28)
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#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 32)
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#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 32)
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#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 32)
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#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 32)
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#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 32)
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#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 36)
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#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 36)
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#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 36)
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#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 36)
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#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 0)
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#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 0)
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#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 0)
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#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 0)
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#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 0)
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#define S3C64XX_GPH9_OUTPUT (0x01 << 4)
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#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 4)
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#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 4)
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#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 4)
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#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 4)
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