Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: amd64_edac: Cleanup return type of amd64_determine_edac_cap() amd64_edac: Add a fix for Erratum 505 EDAC, MCE, AMD: Simplify NB MCE decoder interface EDAC, MCE, AMD: Drop local coreid reporting EDAC, MCE, AMD: Print valid addr when reporting an error EDAC, MCE, AMD: Print CPU number when reporting the error
This commit is contained in:
Linus Torvalds
commit
b48aeab65e
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@ -114,10 +114,22 @@ static int f10_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
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return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
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}
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/*
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* Select DCT to which PCI cfg accesses are routed
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*/
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static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
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{
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u32 reg = 0;
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amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®);
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reg &= 0xfffffffe;
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reg |= dct;
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amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
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}
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static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
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const char *func)
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{
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u32 reg = 0;
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u8 dct = 0;
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if (addr >= 0x140 && addr <= 0x1a0) {
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@ -125,10 +137,7 @@ static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
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addr -= 0x100;
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}
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amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®);
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reg &= 0xfffffffe;
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reg |= dct;
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amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
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f15h_select_dct(pvt, dct);
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return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
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}
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@ -198,6 +207,10 @@ static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
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if (boot_cpu_data.x86 == 0xf)
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min_scrubrate = 0x0;
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/* F15h Erratum #505 */
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if (boot_cpu_data.x86 == 0x15)
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f15h_select_dct(pvt, 0);
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return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate);
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}
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@ -207,6 +220,10 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
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u32 scrubval = 0;
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int i, retval = -EINVAL;
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/* F15h Erratum #505 */
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if (boot_cpu_data.x86 == 0x15)
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f15h_select_dct(pvt, 0);
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amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
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scrubval = scrubval & 0x001F;
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@ -751,10 +768,10 @@ static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
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* Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
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* are ECC capable.
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*/
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static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt)
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static unsigned long amd64_determine_edac_cap(struct amd64_pvt *pvt)
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{
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u8 bit;
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enum dev_type edac_cap = EDAC_FLAG_NONE;
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unsigned long edac_cap = EDAC_FLAG_NONE;
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bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= K8_REV_F)
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? 19
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@ -1953,11 +1970,9 @@ static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
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amd64_handle_ue(mci, m);
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}
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void amd64_decode_bus_error(int node_id, struct mce *m, u32 nbcfg)
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void amd64_decode_bus_error(int node_id, struct mce *m)
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{
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struct mem_ctl_info *mci = mcis[node_id];
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__amd64_decode_bus_error(mci, m);
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__amd64_decode_bus_error(mcis[node_id], m);
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}
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/*
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@ -9,7 +9,7 @@ static u8 xec_mask = 0xf;
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static u8 nb_err_cpumask = 0xf;
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static bool report_gart_errors;
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static void (*nb_bus_decoder)(int node_id, struct mce *m, u32 nbcfg);
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static void (*nb_bus_decoder)(int node_id, struct mce *m);
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void amd_report_gart_errors(bool v)
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{
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@ -17,13 +17,13 @@ void amd_report_gart_errors(bool v)
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}
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EXPORT_SYMBOL_GPL(amd_report_gart_errors);
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void amd_register_ecc_decoder(void (*f)(int, struct mce *, u32))
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void amd_register_ecc_decoder(void (*f)(int, struct mce *))
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{
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nb_bus_decoder = f;
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}
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EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
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void amd_unregister_ecc_decoder(void (*f)(int, struct mce *, u32))
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void amd_unregister_ecc_decoder(void (*f)(int, struct mce *))
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{
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if (nb_bus_decoder) {
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WARN_ON(nb_bus_decoder != f);
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@ -592,31 +592,14 @@ static bool nb_noop_mce(u16 ec, u8 xec)
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return false;
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}
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void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
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void amd_decode_nb_mce(struct mce *m)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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u16 ec = EC(m->status);
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u8 xec = XEC(m->status, 0x1f);
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u32 nbsh = (u32)(m->status >> 32);
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int core = -1;
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int node_id = amd_get_nb_id(m->extcpu);
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u16 ec = EC(m->status);
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u8 xec = XEC(m->status, 0x1f);
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pr_emerg(HW_ERR "Northbridge Error (node %d", node_id);
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/* F10h, revD can disable ErrCpu[3:0] through ErrCpuVal */
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if (c->x86 == 0x10 && c->x86_model > 7) {
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if (nbsh & NBSH_ERR_CPU_VAL)
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core = nbsh & nb_err_cpumask;
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} else {
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u8 assoc_cpus = nbsh & nb_err_cpumask;
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if (assoc_cpus > 0)
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core = fls(assoc_cpus) - 1;
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}
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if (core >= 0)
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pr_cont(", core %d): ", core);
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else
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pr_cont("): ");
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pr_emerg(HW_ERR "Northbridge Error (node %d): ", node_id);
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switch (xec) {
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case 0x2:
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@ -648,7 +631,7 @@ void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
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if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x15)
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if ((xec == 0x8 || xec == 0x0) && nb_bus_decoder)
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nb_bus_decoder(node_id, m, nbcfg);
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nb_bus_decoder(node_id, m);
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return;
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@ -764,13 +747,13 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
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{
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struct mce *m = (struct mce *)data;
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struct cpuinfo_x86 *c = &boot_cpu_data;
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int node, ecc;
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int ecc;
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if (amd_filter_mce(m))
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return NOTIFY_STOP;
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pr_emerg(HW_ERR "MC%d_STATUS[%s|%s|%s|%s|%s",
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m->bank,
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pr_emerg(HW_ERR "CPU:%d\tMC%d_STATUS[%s|%s|%s|%s|%s",
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m->extcpu, m->bank,
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((m->status & MCI_STATUS_OVER) ? "Over" : "-"),
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((m->status & MCI_STATUS_UC) ? "UE" : "CE"),
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((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"),
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@ -789,6 +772,8 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
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pr_cont("]: 0x%016llx\n", m->status);
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if (m->status & MCI_STATUS_ADDRV)
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pr_emerg(HW_ERR "\tMC%d_ADDR: 0x%016llx\n", m->bank, m->addr);
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switch (m->bank) {
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case 0:
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@ -811,8 +796,7 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
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break;
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case 4:
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node = amd_get_nb_id(m->extcpu);
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amd_decode_nb_mce(node, m, 0);
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amd_decode_nb_mce(m);
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break;
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case 5:
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@ -86,9 +86,9 @@ struct amd_decoder_ops {
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};
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void amd_report_gart_errors(bool);
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void amd_register_ecc_decoder(void (*f)(int, struct mce *, u32));
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void amd_unregister_ecc_decoder(void (*f)(int, struct mce *, u32));
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void amd_decode_nb_mce(int, struct mce *, u32);
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void amd_register_ecc_decoder(void (*f)(int, struct mce *));
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void amd_unregister_ecc_decoder(void (*f)(int, struct mce *));
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void amd_decode_nb_mce(struct mce *);
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int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data);
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#endif /* _EDAC_MCE_AMD_H */
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