usb: dwc2: Delayed status support
Added delayed status support for Control transfers. Tested in all 3 modes: Slave, BDMA and DDMA. Performed tests: USB CV (Ch9 and MSC), Control Read/Write tests using Synopsys USB test environment function driver. Signed-off-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>hifive-unleashed-5.2
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c67d4262f6
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b4c53b4ac6
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@ -993,6 +993,7 @@ struct dwc2_hregs_backup {
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* @ctrl_buff: Buffer for EP0 control requests.
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* @ctrl_buff: Buffer for EP0 control requests.
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* @ctrl_req: Request for EP0 control packets.
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* @ctrl_req: Request for EP0 control packets.
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* @ep0_state: EP0 control transfers state
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* @ep0_state: EP0 control transfers state
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* @delayed_status: true when gadget driver asks for delayed status
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* @test_mode: USB test mode requested by the host
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* @test_mode: USB test mode requested by the host
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* @remote_wakeup_allowed: True if device is allowed to wake-up host by
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* @remote_wakeup_allowed: True if device is allowed to wake-up host by
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* remote-wakeup signalling
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* remote-wakeup signalling
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@ -1175,6 +1176,7 @@ struct dwc2_hsotg {
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void *ep0_buff;
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void *ep0_buff;
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void *ctrl_buff;
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void *ctrl_buff;
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enum dwc2_ep0_state ep0_state;
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enum dwc2_ep0_state ep0_state;
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unsigned delayed_status : 1;
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u8 test_mode;
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u8 test_mode;
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dma_addr_t setup_desc_dma[2];
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dma_addr_t setup_desc_dma[2];
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@ -27,6 +27,8 @@
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#include <linux/usb/ch9.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/phy.h>
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#include <linux/usb/phy.h>
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#include <linux/usb/composite.h>
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#include "core.h"
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#include "core.h"
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#include "hw.h"
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#include "hw.h"
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@ -1446,6 +1448,11 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
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return 0;
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return 0;
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}
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}
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/* Change EP direction if status phase request is after data out */
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if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
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hs->ep0_state == DWC2_EP0_DATA_OUT)
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hs_ep->dir_in = 1;
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if (first) {
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if (first) {
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if (!hs_ep->isochronous) {
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if (!hs_ep->isochronous) {
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dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
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dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
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@ -1938,6 +1945,10 @@ static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
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dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
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dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
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}
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}
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hsotg->delayed_status = false;
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if (ret == USB_GADGET_DELAYED_STATUS)
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hsotg->delayed_status = true;
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/*
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/*
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* the request is either unhandlable, or is not formatted correctly
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* the request is either unhandlable, or is not formatted correctly
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* so respond with a STALL for the status stage to indicate failure.
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* so respond with a STALL for the status stage to indicate failure.
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@ -2387,8 +2398,8 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
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if (!using_desc_dma(hsotg) && epnum == 0 &&
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if (!using_desc_dma(hsotg) && epnum == 0 &&
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hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
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hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
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/* Move to STATUS IN */
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/* Move to STATUS IN */
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dwc2_hsotg_ep0_zlp(hsotg, true);
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if (!hsotg->delayed_status)
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return;
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dwc2_hsotg_ep0_zlp(hsotg, true);
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}
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}
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/*
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/*
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@ -3053,8 +3064,20 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
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/* Safety check EP0 state when STSPHSERCVD asserted */
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/* Safety check EP0 state when STSPHSERCVD asserted */
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if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
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if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
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/* Move to STATUS IN for DDMA */
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/* Move to STATUS IN for DDMA */
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if (using_desc_dma(hsotg))
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if (using_desc_dma(hsotg)) {
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dwc2_hsotg_ep0_zlp(hsotg, true);
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if (!hsotg->delayed_status)
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dwc2_hsotg_ep0_zlp(hsotg, true);
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else
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/* In case of 3 stage Control Write with delayed
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* status, when Status IN transfer started
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* before STSPHSERCVD asserted, NAKSTS bit not
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* cleared by CNAK in dwc2_hsotg_start_req()
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* function. Clear now NAKSTS to allow complete
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* transfer.
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*/
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dwc2_set_bit(hsotg, DIEPCTL(0),
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DXEPCTL_CNAK);
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}
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}
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}
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}
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}
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