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pinctrl: tegra: Support 32 bit register access 

Tegra194 chip has 32 bit pinctrl registers. Existing register defines in
header are only 16 bit.
Modified common pinctrl-tegra driver to support 32 bit registers of
Tegra 194 and later chips.

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
alistair/sunxi64-5.4-dsi
Krishna Yarlagadda 2019-05-16 17:23:12 +05:30 committed by Linus Walleij
parent 2585a584f8
commit b4e18ba27e
2 changed files with 8 additions and 8 deletions
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8
drivers/pinctrl/tegra/pinctrl-tegra.c
View File

@ -292,7 +292,7 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
const struct tegra_pingroup *g,
enum tegra_pinconf_param param,
bool report_err,
s8 *bank, s16 *reg, s8 *bit, s8 *width)
s8 *bank, s32 *reg, s8 *bit, s8 *width)
{
switch (param) {
case TEGRA_PINCONF_PARAM_PULL:
@ -451,7 +451,7 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
const struct tegra_pingroup *g;
int ret;
s8 bank, bit, width;
s16 reg;
s32 reg;
u32 val, mask;
g = &pmx->soc->groups[group];
@ -480,7 +480,7 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
const struct tegra_pingroup *g;
int ret, i;
s8 bank, bit, width;
s16 reg;
s32 reg;
u32 val, mask;
g = &pmx->soc->groups[group];
@ -548,7 +548,7 @@ static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
const struct tegra_pingroup *g;
int i, ret;
s8 bank, bit, width;
s16 reg;
s32 reg;
u32 val;
g = &pmx->soc->groups[group];

8
drivers/pinctrl/tegra/pinctrl-tegra.h
View File

@ -143,10 +143,10 @@ struct tegra_pingroup {
const unsigned *pins;
u8 npins;
u8 funcs[4];
s16 mux_reg;
s16 pupd_reg;
s16 tri_reg;
s16 drv_reg;
s32 mux_reg;
s32 pupd_reg;
s32 tri_reg;
s32 drv_reg;
u32 mux_bank:2;
u32 pupd_bank:2;
u32 tri_bank:2;