irq_domain/x86: Convert x86 (embedded) to use common irq_domain
This patch removes the x86-specific definition of irq_domain and replaces it with the common implementation. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Thomas Gleixner <tglx@linutronix.de>hifive-unleashed-5.1
Grant Likely
parent
6d166fec12
commit
b4e518547d
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@ -398,6 +398,7 @@ config X86_INTEL_CE
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select X86_REBOOTFIXUPS
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select OF
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select OF_EARLY_FLATTREE
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select IRQ_DOMAIN
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---help---
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Select for the Intel CE media processor (CE4100) SOC.
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This option compiles in support for the CE4100 SOC for settop
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@ -2076,6 +2077,7 @@ config OLPC
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select GPIOLIB
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select OF
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select OF_PROMTREE
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select IRQ_DOMAIN
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---help---
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Add support for detecting the unique features of the OLPC
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XO hardware.
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@ -1,12 +0,0 @@
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#ifndef __IRQ_CONTROLLER__
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#define __IRQ_CONTROLLER__
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struct irq_domain {
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int (*xlate)(struct irq_domain *h, const u32 *intspec, u32 intsize,
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u32 *out_hwirq, u32 *out_type);
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void *priv;
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struct device_node *controller;
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struct list_head l;
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};
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#endif
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@ -21,7 +21,6 @@
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#include <asm/irq.h>
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#include <linux/atomic.h>
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#include <asm/setup.h>
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#include <asm/irq_controller.h>
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#ifdef CONFIG_OF
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extern int of_ioapic;
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@ -43,15 +42,6 @@ extern char cmd_line[COMMAND_LINE_SIZE];
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#define pci_address_to_pio pci_address_to_pio
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unsigned long pci_address_to_pio(phys_addr_t addr);
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/**
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* irq_dispose_mapping - Unmap an interrupt
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* @virq: linux virq number of the interrupt to unmap
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*
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* FIXME: We really should implement proper virq handling like power,
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* but that's going to be major surgery.
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*/
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static inline void irq_dispose_mapping(unsigned int virq) { }
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#define HAVE_ARCH_DEVTREE_FIXUPS
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#endif /* __ASSEMBLY__ */
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@ -4,6 +4,7 @@
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#include <linux/bootmem.h>
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/of.h>
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@ -17,64 +18,14 @@
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#include <linux/initrd.h>
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#include <asm/hpet.h>
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#include <asm/irq_controller.h>
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#include <asm/apic.h>
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#include <asm/pci_x86.h>
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__initdata u64 initial_dtb;
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char __initdata cmd_line[COMMAND_LINE_SIZE];
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static LIST_HEAD(irq_domains);
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static DEFINE_RAW_SPINLOCK(big_irq_lock);
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int __initdata of_ioapic;
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#ifdef CONFIG_X86_IO_APIC
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static void add_interrupt_host(struct irq_domain *ih)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&big_irq_lock, flags);
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list_add(&ih->l, &irq_domains);
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raw_spin_unlock_irqrestore(&big_irq_lock, flags);
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}
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#endif
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static struct irq_domain *get_ih_from_node(struct device_node *controller)
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{
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struct irq_domain *ih, *found = NULL;
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unsigned long flags;
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raw_spin_lock_irqsave(&big_irq_lock, flags);
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list_for_each_entry(ih, &irq_domains, l) {
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if (ih->controller == controller) {
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found = ih;
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break;
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}
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}
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raw_spin_unlock_irqrestore(&big_irq_lock, flags);
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return found;
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}
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unsigned int irq_create_of_mapping(struct device_node *controller,
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const u32 *intspec, unsigned int intsize)
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{
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struct irq_domain *ih;
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u32 virq, type;
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int ret;
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ih = get_ih_from_node(controller);
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if (!ih)
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return 0;
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ret = ih->xlate(ih, intspec, intsize, &virq, &type);
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if (ret)
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return 0;
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if (type == IRQ_TYPE_NONE)
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return virq;
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irq_set_irq_type(virq, type);
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return virq;
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}
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EXPORT_SYMBOL_GPL(irq_create_of_mapping);
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unsigned long pci_address_to_pio(phys_addr_t address)
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{
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/*
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@ -354,36 +305,43 @@ static struct of_ioapic_type of_ioapic_type[] =
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},
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};
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static int ioapic_xlate(struct irq_domain *id, const u32 *intspec, u32 intsize,
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u32 *out_hwirq, u32 *out_type)
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static int ioapic_xlate(struct irq_domain *domain,
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struct device_node *controller,
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const u32 *intspec, u32 intsize,
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irq_hw_number_t *out_hwirq, u32 *out_type)
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{
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struct mp_ioapic_gsi *gsi_cfg;
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struct io_apic_irq_attr attr;
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struct of_ioapic_type *it;
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u32 line, idx, type;
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u32 line, idx;
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int rc;
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if (intsize < 2)
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if (WARN_ON(intsize < 2))
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return -EINVAL;
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line = *intspec;
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idx = (u32) id->priv;
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gsi_cfg = mp_ioapic_gsi_routing(idx);
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*out_hwirq = line + gsi_cfg->gsi_base;
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line = intspec[0];
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intspec++;
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type = *intspec;
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if (type >= ARRAY_SIZE(of_ioapic_type))
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if (intspec[1] >= ARRAY_SIZE(of_ioapic_type))
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return -EINVAL;
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it = of_ioapic_type + type;
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*out_type = it->out_type;
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it = &of_ioapic_type[intspec[1]];
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idx = (u32) domain->host_data;
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set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);
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return io_apic_setup_irq_pin_once(*out_hwirq, cpu_to_node(0), &attr);
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rc = io_apic_setup_irq_pin_once(irq_find_mapping(domain, line),
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cpu_to_node(0), &attr);
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if (rc)
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return rc;
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*out_hwirq = line;
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*out_type = it->out_type;
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return 0;
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}
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const struct irq_domain_ops ioapic_irq_domain_ops = {
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.xlate = ioapic_xlate,
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};
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static void __init ioapic_add_ofnode(struct device_node *np)
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{
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struct resource r;
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@ -399,13 +357,14 @@ static void __init ioapic_add_ofnode(struct device_node *np)
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for (i = 0; i < nr_ioapics; i++) {
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if (r.start == mpc_ioapic_addr(i)) {
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struct irq_domain *id;
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struct mp_ioapic_gsi *gsi_cfg;
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id = kzalloc(sizeof(*id), GFP_KERNEL);
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gsi_cfg = mp_ioapic_gsi_routing(i);
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id = irq_domain_add_legacy(np, 32, gsi_cfg->gsi_base, 0,
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&ioapic_irq_domain_ops,
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(void*)i);
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BUG_ON(!id);
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id->controller = np;
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id->xlate = ioapic_xlate;
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id->priv = (void *)i;
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add_interrupt_host(id);
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return;
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}
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}
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@ -255,13 +255,13 @@ static inline int __init mdio_ofgpio_init(void)
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return platform_driver_register(&mdio_ofgpio_driver);
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}
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static inline void __exit mdio_ofgpio_exit(void)
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static inline void mdio_ofgpio_exit(void)
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{
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platform_driver_unregister(&mdio_ofgpio_driver);
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}
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#else
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static inline int __init mdio_ofgpio_init(void) { return 0; }
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static inline void __exit mdio_ofgpio_exit(void) { }
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static inline void mdio_ofgpio_exit(void) { }
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#endif /* CONFIG_OF_GPIO */
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static struct platform_driver mdio_gpio_driver = {
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