drm/radeon/kms: add regs and irq tracking bits for hpd
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
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@ -558,6 +558,7 @@
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# define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19)
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# define DC_I2C_SW_DONE_INTERRUPT (1 << 20)
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# define DC_I2C_HW_DONE_INTERRUPT (1 << 21)
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#define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8
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#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8
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# define DC_HPD4_INTERRUPT (1 << 14)
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# define DC_HPD4_RX_INTERRUPT (1 << 15)
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@ -590,6 +591,18 @@
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# define DC_HPD6_INTERRUPT (1 << 21)
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# define DC_HPD6_RX_INTERRUPT (1 << 22)
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#define DACA_AUTO_DETECT_CONTROL 0x7828
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#define DACB_AUTO_DETECT_CONTROL 0x7a28
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#define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028
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#define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128
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# define DACx_AUTODETECT_MODE(x) ((x) << 0)
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# define DACx_AUTODETECT_MODE_NONE 0
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# define DACx_AUTODETECT_MODE_CONNECT 1
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# define DACx_AUTODETECT_MODE_DISCONNECT 2
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# define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8)
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/* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */
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# define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16)
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#define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038
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#define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138
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#define DACA_AUTODETECT_INT_CONTROL 0x7838
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@ -597,23 +610,62 @@
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# define DACx_AUTODETECT_ACK (1 << 0)
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# define DACx_AUTODETECT_INT_ENABLE (1 << 16)
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#define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00
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#define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10
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#define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24
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# define DC_HOT_PLUG_DETECTx_EN (1 << 0)
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#define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04
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#define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14
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#define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28
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# define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0)
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# define DC_HOT_PLUG_DETECTx_SENSE (1 << 1)
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/* DCE 3.0 */
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#define DC_HPD1_INT_STATUS 0x7d00
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#define DC_HPD2_INT_STATUS 0x7d0c
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#define DC_HPD3_INT_STATUS 0x7d18
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#define DC_HPD4_INT_STATUS 0x7d24
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/* DCE 3.2 */
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#define DC_HPD5_INT_STATUS 0x7dc0
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#define DC_HPD6_INT_STATUS 0x7df4
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# define DC_HPDx_INT_STATUS (1 << 0)
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# define DC_HPDx_SENSE (1 << 1)
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# define DC_HPDx_RX_INT_STATUS (1 << 8)
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#define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08
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#define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18
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#define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c
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# define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0)
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# define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8)
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# define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16)
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/* DCE 3.2 */
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/* DCE 3.0 */
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#define DC_HPD1_INT_CONTROL 0x7d04
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#define DC_HPD2_INT_CONTROL 0x7d10
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#define DC_HPD3_INT_CONTROL 0x7d1c
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#define DC_HPD4_INT_CONTROL 0x7d28
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/* DCE 3.2 */
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#define DC_HPD5_INT_CONTROL 0x7dc4
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#define DC_HPD6_INT_CONTROL 0x7df8
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# define DC_HPDx_INT_ACK (1 << 0)
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# define DC_HPDx_INT_POLARITY (1 << 8)
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# define DC_HPDx_INT_EN (1 << 16)
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# define DC_HPDx_RX_INT_ACK (1 << 20)
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# define DC_HPDx_RX_INT_EN (1 << 24)
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/* DCE 3.0 */
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#define DC_HPD1_CONTROL 0x7d08
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#define DC_HPD2_CONTROL 0x7d14
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#define DC_HPD3_CONTROL 0x7d20
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#define DC_HPD4_CONTROL 0x7d2c
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/* DCE 3.2 */
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#define DC_HPD5_CONTROL 0x7dc8
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#define DC_HPD6_CONTROL 0x7dfc
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# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
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# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
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/* DCE 3.2 */
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# define DC_HPDx_EN (1 << 28)
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/*
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* PM4
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*/
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@ -339,6 +339,8 @@ struct radeon_irq {
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bool sw_int;
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/* FIXME: use a define max crtc rather than hardcode it */
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bool crtc_vblank_int[2];
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/* FIXME: use defines for max hpd/dacs */
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bool hpd[6];
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spinlock_t sw_lock;
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int sw_refcount;
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};
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@ -887,6 +887,7 @@
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# define RADEON_FP_PANEL_FORMAT (1 << 3)
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# define RADEON_FP_EN_TMDS (1 << 7)
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# define RADEON_FP_DETECT_SENSE (1 << 8)
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# define RADEON_FP_DETECT_INT_POL (1 << 9)
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# define R200_FP_SOURCE_SEL_MASK (3 << 10)
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# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
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# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
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@ -894,6 +895,7 @@
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# define R200_FP_SOURCE_SEL_TRANS (3 << 10)
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# define RADEON_FP_SEL_CRTC1 (0 << 13)
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# define RADEON_FP_SEL_CRTC2 (1 << 13)
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# define R300_HPD_SEL(x) ((x) << 13)
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# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
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# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
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# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
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@ -909,6 +911,7 @@
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# define RADEON_FP2_ON (1 << 2)
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# define RADEON_FP2_PANEL_FORMAT (1 << 3)
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# define RADEON_FP2_DETECT_SENSE (1 << 8)
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# define RADEON_FP2_DETECT_INT_POL (1 << 9)
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# define R200_FP2_SOURCE_SEL_MASK (3 << 10)
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# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)
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# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)
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@ -988,14 +991,20 @@
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#define RADEON_GEN_INT_CNTL 0x0040
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# define RADEON_CRTC_VBLANK_MASK (1 << 0)
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# define RADEON_FP_DETECT_MASK (1 << 4)
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# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
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# define RADEON_FP2_DETECT_MASK (1 << 10)
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# define RADEON_SW_INT_ENABLE (1 << 25)
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#define RADEON_GEN_INT_STATUS 0x0044
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# define AVIVO_DISPLAY_INT_STATUS (1 << 0)
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# define RADEON_CRTC_VBLANK_STAT (1 << 0)
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# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
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# define RADEON_FP_DETECT_STAT (1 << 4)
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# define RADEON_FP_DETECT_STAT_ACK (1 << 4)
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# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
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# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
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# define RADEON_FP2_DETECT_STAT (1 << 10)
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# define RADEON_FP2_DETECT_STAT_ACK (1 << 10)
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# define RADEON_SW_INT_FIRE (1 << 26)
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# define RADEON_SW_INT_TEST (1 << 25)
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# define RADEON_SW_INT_TEST_ACK (1 << 25)
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@ -30,27 +30,12 @@
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/* Registers */
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#define R_000040_GEN_INT_CNTL 0x000040
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#define S_000040_DISPLAY_INT_STATUS(x) (((x) & 0x1) << 0)
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#define G_000040_DISPLAY_INT_STATUS(x) (((x) >> 0) & 0x1)
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#define C_000040_DISPLAY_INT_STATUS 0xFFFFFFFE
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#define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12)
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#define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1)
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#define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF
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#define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6)
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#define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1)
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#define C_000040_CRTC2_VSYNC 0xFFFFFFBF
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#define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7)
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#define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1)
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#define C_000040_SNAPSHOT2 0xFFFFFF7F
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#define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9)
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#define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1)
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#define C_000040_CRTC2_VBLANK 0xFFFFFDFF
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#define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10)
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#define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1)
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#define C_000040_FP2_DETECT 0xFFFFFBFF
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#define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11)
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#define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1)
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#define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF
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#define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18)
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#define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1)
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#define C_000040_SCRATCH_INT_MASK 0xFFFBFFFF
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#define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19)
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#define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1)
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#define C_000040_GUI_IDLE_MASK 0xFFF7FFFF
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#define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13)
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#define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1)
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#define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF
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#define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5)
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#define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1)
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#define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF
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#define S_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 16)
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#define G_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) >> 16) & 0x1)
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#define C_007EDC_DACA_AUTODETECT_INTERRUPT 0xFFFEFFFF
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#define S_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 17)
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#define G_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) >> 17) & 0x1)
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#define C_007EDC_DACB_AUTODETECT_INTERRUPT 0xFFFDFFFF
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#define S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) & 0x1) << 18)
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#define G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) >> 18) & 0x1)
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#define C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT 0xFFFBFFFF
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#define S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) & 0x1) << 19)
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#define G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) >> 19) & 0x1)
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#define C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT 0xFFF7FFFF
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#define R_007828_DACA_AUTODETECT_CONTROL 0x007828
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#define S_007828_DACA_AUTODETECT_MODE(x) (((x) & 0x3) << 0)
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#define G_007828_DACA_AUTODETECT_MODE(x) (((x) >> 0) & 0x3)
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#define C_007828_DACA_AUTODETECT_MODE 0xFFFFFFFC
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#define S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)
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#define G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)
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#define C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF
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#define S_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16)
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#define G_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3)
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#define C_007828_DACA_AUTODETECT_CHECK_MASK 0xFFFCFFFF
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#define R_007838_DACA_AUTODETECT_INT_CONTROL 0x007838
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#define S_007838_DACA_AUTODETECT_ACK(x) (((x) & 0x1) << 0)
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#define C_007838_DACA_DACA_AUTODETECT_ACK 0xFFFFFFFE
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#define S_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16)
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#define G_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1)
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#define C_007838_DACA_AUTODETECT_INT_ENABLE 0xFFFCFFFF
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#define R_007A28_DACB_AUTODETECT_CONTROL 0x007A28
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#define S_007A28_DACB_AUTODETECT_MODE(x) (((x) & 0x3) << 0)
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#define G_007A28_DACB_AUTODETECT_MODE(x) (((x) >> 0) & 0x3)
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#define C_007A28_DACB_AUTODETECT_MODE 0xFFFFFFFC
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#define S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)
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#define G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)
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#define C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF
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#define S_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16)
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#define G_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3)
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#define C_007A28_DACB_AUTODETECT_CHECK_MASK 0xFFFCFFFF
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#define R_007A38_DACB_AUTODETECT_INT_CONTROL 0x007A38
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#define S_007A38_DACB_AUTODETECT_ACK(x) (((x) & 0x1) << 0)
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#define C_007A38_DACB_DACA_AUTODETECT_ACK 0xFFFFFFFE
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#define S_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16)
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#define G_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1)
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#define C_007A38_DACB_AUTODETECT_INT_ENABLE 0xFFFCFFFF
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#define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL 0x007D00
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#define S_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) & 0x1) << 0)
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#define G_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) >> 0) & 0x1)
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#define C_007D00_DC_HOT_PLUG_DETECT1_EN 0xFFFFFFFE
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#define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0x007D04
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#define S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) & 0x1) << 0)
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#define G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) >> 0) & 0x1)
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#define C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0xFFFFFFFE
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#define S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) & 0x1) << 1)
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#define G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) >> 1) & 0x1)
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#define C_007D04_DC_HOT_PLUG_DETECT1_SENSE 0xFFFFFFFD
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#define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL 0x007D08
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#define S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x) (((x) & 0x1) << 0)
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#define C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK 0xFFFFFFFE
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#define S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) & 0x1) << 8)
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#define G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) >> 8) & 0x1)
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#define C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY 0xFFFFFEFF
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#define S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) & 0x1) << 16)
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#define G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) >> 16) & 0x1)
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#define C_007D08_DC_HOT_PLUG_DETECT1_INT_EN 0xFFFEFFFF
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#define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL 0x007D10
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#define S_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) & 0x1) << 0)
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#define G_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) >> 0) & 0x1)
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#define C_007D10_DC_HOT_PLUG_DETECT2_EN 0xFFFFFFFE
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#define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0x007D14
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#define S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) & 0x1) << 0)
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#define G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) >> 0) & 0x1)
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#define C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0xFFFFFFFE
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#define S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) & 0x1) << 1)
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#define G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) >> 1) & 0x1)
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#define C_007D14_DC_HOT_PLUG_DETECT2_SENSE 0xFFFFFFFD
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#define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL 0x007D18
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#define S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x) (((x) & 0x1) << 0)
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#define C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK 0xFFFFFFFE
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#define S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) & 0x1) << 8)
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#define G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) >> 8) & 0x1)
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#define C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY 0xFFFFFEFF
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#define S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) & 0x1) << 16)
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#define G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) >> 16) & 0x1)
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#define C_007D18_DC_HOT_PLUG_DETECT2_INT_EN 0xFFFEFFFF
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/* MC registers */
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#define R_000000_MC_STATUS 0x000000
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Loading…
Reference in a new issue