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drm/rockchip: vop: no need wait vblank on crtc enable 

Since atomic framework, crtc enable and disable are in pairs,
no need to wait vblank.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Reviewed-by: Sandy huang <sandy.huang@rock-chips.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1501494577-6884-1-git-send-email-mark.yao@rock-chips.com
hifive-unleashed-5.1
Mark yao 2017-07-31 17:49:37 +08:00 committed by Mark Yao
parent f461bd2b49
commit b5015e92a0
1 changed files with 0 additions and 36 deletions
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36
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
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@ -895,42 +895,6 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
return;
}
/*
* If dclk rate is zero, mean that scanout is stop,
* we don't need wait any more.
*/
if (clk_get_rate(vop->dclk)) {
/*
* Rk3288 vop timing register is immediately, when configure
* display timing on display time, may cause tearing.
*
* Vop standby will take effect at end of current frame,
* if dsp hold valid irq happen, it means standby complete.
*
* mode set:
* standby and wait complete --> |----
* | display time
* |----
* |---> dsp hold irq
* configure display timing --> |
* standby exit |
* | new frame start.
*/
reinit_completion(&vop->dsp_hold_completion);
vop_dsp_hold_valid_irq_enable(vop);
spin_lock(&vop->reg_lock);
VOP_REG_SET(vop, common, standby, 1);
spin_unlock(&vop->reg_lock);
wait_for_completion(&vop->dsp_hold_completion);
vop_dsp_hold_valid_irq_disable(vop);
}
pin_pol = BIT(DCLK_INVERT);
pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
BIT(HSYNC_POSITIVE) : 0;