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clk: qcom: ipq4019: correct sdcc frequency and parent name 

1. The parent for sdcc clock is sdccpll.
2. The frequency value was wrong so modified the same.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
hifive-unleashed-5.1
Abhishek Sahu 2016-11-25 21:11:31 +05:30 committed by Stephen Boyd
parent 5c1a96935f
commit b52a0c2c11
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/qcom/gcc-ipq4019.c
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@ -124,7 +124,7 @@ static struct parent_map gcc_xo_sdcc1_500_map[] = {
static const char * const gcc_xo_sdcc1_500[] = {
"xo",
"ddrpll",
"ddrpllsdcc",
"fepll500",
};
@ -549,7 +549,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
F(25000000, P_FEPLL500, 1, 1, 20),
F(50000000, P_FEPLL500, 1, 1, 10),
F(100000000, P_FEPLL500, 1, 1, 5),
F(193000000, P_DDRPLL, 1, 0, 0),
F(192000000, P_DDRPLL, 1, 0, 0),
{ }
};