drm/radeon/cik: add srbm_select function
Allows us to select instanced registers based on: - ME (micro engine - Pipe - Queue - VMID Switch MC setup to use this new function. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -163,6 +163,29 @@ static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
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{0x0000009f, 0x00b48000}
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};
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/**
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* cik_srbm_select - select specific register instances
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*
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* @rdev: radeon_device pointer
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* @me: selected ME (micro engine)
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* @pipe: pipe
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* @queue: queue
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* @vmid: VMID
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*
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* Switches the currently active registers instances. Some
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* registers are instanced per VMID, others are instanced per
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* me/pipe/queue combination.
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*/
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static void cik_srbm_select(struct radeon_device *rdev,
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u32 me, u32 pipe, u32 queue, u32 vmid)
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{
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u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |
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MEID(me & 0x3) |
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VMID(vmid & 0xf) |
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QUEUEID(queue & 0x7));
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WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl);
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}
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/* ucode loading */
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/**
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* ci_mc_load_microcode - load MC ucode into the hw
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@ -3351,7 +3374,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
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/* XXX SH_MEM regs */
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/* where to put LDS, scratch, GPUVM in FSA64 space */
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for (i = 0; i < 16; i++) {
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WREG32(SRBM_GFX_CNTL, VMID(i));
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cik_srbm_select(rdev, 0, 0, 0, i);
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/* CP and shaders */
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WREG32(SH_MEM_CONFIG, 0);
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WREG32(SH_MEM_APE1_BASE, 1);
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@ -3364,7 +3387,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
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WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0);
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/* XXX SDMA RLC - todo */
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}
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WREG32(SRBM_GFX_CNTL, 0);
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cik_srbm_select(rdev, 0, 0, 0, 0);
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cik_pcie_gart_tlb_flush(rdev);
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DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
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