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Patches for MSM core 

These patches are changes to the MSM timer code that will be for
 upcoming targets, including a generalization of the binding and
 preventing a missing timer interrupt.
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Merge tag 'msm-core-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm into next/soc

From David Brown:
Patches for MSM core

These patches are changes to the MSM timer code that will be for
upcoming targets, including a generalization of the binding and
preventing a missing timer interrupt.

* tag 'msm-core-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm:
  ARM: msm: Wait for timer clear to complete
  ARM: msm: Rework timer binding to be more general

Signed-off-by: Olof Johansson <olof@lixom.net>
hifive-unleashed-5.1
Olof Johansson 2013-04-14 20:49:21 -07:00
parent 56c5c13f70 e25e3d1fef
commit b56a7f9206
4 changed files with 86 additions and 107 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
Documentation/devicetree/bindings/arm/msm/timer.txt
View File

@ -3,36 +3,35 @@
Properties:
- compatible : Should at least contain "qcom,msm-timer". More specific
properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
purpose timer and a debug timer respectively.
properties specify which subsystem the timers are paired with.
- interrupts : Interrupt indicating a match event.
"qcom,kpss-timer" - krait subsystem
"qcom,scss-timer" - scorpion subsystem
- reg : Specifies the base address of the timer registers. The second region
specifies an optional register used to configure the clock divider.
- interrupts : Interrupts for the the debug timer, the first general purpose
timer, and optionally a second general purpose timer in that
order.
- clock-frequency : The frequency of the timer in Hz.
- reg : Specifies the base address of the timer registers.
- clock-frequency : The frequency of the debug timer and the general purpose
timer(s) in Hz in that order.
Optional:
- cpu-offset : per-cpu offset used when the timer is accessed without the
CPU remapping facilities. The offset is cpu-offset * cpu-nr.
CPU remapping facilities. The offset is
cpu-offset + (0x10000 * cpu-nr).
Example:
timer@200a004 {
compatible = "qcom,msm-gpt", "qcom,msm-timer";
interrupts = <1 2 0x301>;
reg = <0x0200a004 0x10>;
clock-frequency = <32768>;
cpu-offset = <0x40000>;
};
timer@200a024 {
compatible = "qcom,msm-dgt", "qcom,msm-timer";
interrupts = <1 3 0x301>;
reg = <0x0200a024 0x10>,
<0x0200a034 0x4>;
clock-frequency = <6750000>;
timer@200a000 {
compatible = "qcom,scss-timer", "qcom,msm-timer";
interrupts = <1 1 0x301>,
<1 2 0x301>,
<1 3 0x301>;
reg = <0x0200a000 0x100>;
clock-frequency = <19200000>,
<32768>;
cpu-offset = <0x40000>;
};

20
arch/arm/boot/dts/msm8660-surf.dts
View File

@ -16,19 +16,13 @@
};
timer@2000004 {
compatible = "qcom,msm-gpt", "qcom,msm-timer";
interrupts = <1 1 0x301>;
reg = <0x02000004 0x10>;
clock-frequency = <32768>;
cpu-offset = <0x40000>;
};
timer@2000024 {
compatible = "qcom,msm-dgt", "qcom,msm-timer";
interrupts = <1 0 0x301>;
reg = <0x02000024 0x10>,
<0x02000034 0x4>;
clock-frequency = <6750000>;
compatible = "qcom,scss-timer", "qcom,msm-timer";
interrupts = <1 0 0x301>,
<1 1 0x301>,
<1 2 0x301>;
reg = <0x02000000 0x100>;
clock-frequency = <27000000>,
<32768>;
cpu-offset = <0x40000>;
};

22
arch/arm/boot/dts/msm8960-cdp.dts
View File

@ -15,20 +15,14 @@
< 0x02002000 0x1000 >;
};
timer@200a004 {
compatible = "qcom,msm-gpt", "qcom,msm-timer";
interrupts = <1 2 0x301>;
reg = <0x0200a004 0x10>;
clock-frequency = <32768>;
cpu-offset = <0x80000>;
};
timer@200a024 {
compatible = "qcom,msm-dgt", "qcom,msm-timer";
interrupts = <1 1 0x301>;
reg = <0x0200a024 0x10>,
<0x0200a034 0x4>;
clock-frequency = <6750000>;
timer@200a000 {
compatible = "qcom,kpss-timer", "qcom,msm-timer";
interrupts = <1 1 0x301>,
<1 2 0x301>,
<1 3 0x301>;
reg = <0x0200a000 0x100>;
clock-frequency = <27000000>,
<32768>;
cpu-offset = <0x80000>;
};

110
arch/arm/mach-msm/timer.c
View File

@ -30,19 +30,22 @@
#include "common.h"
#define TIMER_MATCH_VAL 0x0000
#define TIMER_COUNT_VAL 0x0004
#define TIMER_ENABLE 0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
#define TIMER_ENABLE_EN BIT(0)
#define TIMER_CLEAR 0x000C
#define DGT_CLK_CTL_DIV_4 0x3
#define TIMER_MATCH_VAL 0x0000
#define TIMER_COUNT_VAL 0x0004
#define TIMER_ENABLE 0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
#define TIMER_ENABLE_EN BIT(0)
#define TIMER_CLEAR 0x000C
#define DGT_CLK_CTL 0x10
#define DGT_CLK_CTL_DIV_4 0x3
#define TIMER_STS_GPT0_CLR_PEND BIT(10)
#define GPT_HZ 32768
#define MSM_DGT_SHIFT 5
static void __iomem *event_base;
static void __iomem *sts_base;
static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
@ -67,6 +70,11 @@ static int msm_timer_set_next_event(unsigned long cycles,
writel_relaxed(ctrl, event_base + TIMER_CLEAR);
writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
if (sts_base)
while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
cpu_relax();
writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
return 0;
}
@ -137,9 +145,6 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
if (!smp_processor_id())
return 0;
writel_relaxed(0, event_base + TIMER_ENABLE);
writel_relaxed(0, event_base + TIMER_CLEAR);
writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
evt->irq = msm_clockevent.irq;
evt->name = "local_timer";
evt->features = msm_clockevent.features;
@ -177,9 +182,6 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
struct clocksource *cs = &msm_clocksource;
int res;
writel_relaxed(0, event_base + TIMER_ENABLE);
writel_relaxed(0, event_base + TIMER_CLEAR);
writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
ce->cpumask = cpumask_of(0);
ce->irq = irq;
@ -217,13 +219,9 @@ err:
}
#ifdef CONFIG_OF
static const struct of_device_id msm_dgt_match[] __initconst = {
{ .compatible = "qcom,msm-dgt" },
{ },
};
static const struct of_device_id msm_gpt_match[] __initconst = {
{ .compatible = "qcom,msm-gpt" },
static const struct of_device_id msm_timer_match[] __initconst = {
{ .compatible = "qcom,kpss-timer" },
{ .compatible = "qcom,scss-timer" },
{ },
};
@ -234,33 +232,29 @@ void __init msm_dt_timer_init(void)
int irq;
struct resource res;
u32 percpu_offset;
void __iomem *dgt_clk_ctl;
void __iomem *base;
void __iomem *cpu0_base;
np = of_find_matching_node(NULL, msm_gpt_match);
np = of_find_matching_node(NULL, msm_timer_match);
if (!np) {
pr_err("Can't find GPT DT node\n");
pr_err("Can't find msm timer DT node\n");
return;
}
event_base = of_iomap(np, 0);
if (!event_base) {
base = of_iomap(np, 0);
if (!base) {
pr_err("Failed to map event base\n");
return;
}
irq = irq_of_parse_and_map(np, 0);
/* We use GPT0 for the clockevent */
irq = irq_of_parse_and_map(np, 1);
if (irq <= 0) {
pr_err("Can't get irq\n");
return;
}
of_node_put(np);
np = of_find_matching_node(NULL, msm_dgt_match);
if (!np) {
pr_err("Can't find DGT DT node\n");
return;
}
/* We use CPU0's DGT for the clocksource */
if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
percpu_offset = 0;
@ -269,45 +263,43 @@ void __init msm_dt_timer_init(void)
return;
}
source_base = ioremap(res.start + percpu_offset, resource_size(&res));
if (!source_base) {
cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
if (!cpu0_base) {
pr_err("Failed to map source base\n");
return;
}
if (!of_address_to_resource(np, 1, &res)) {
dgt_clk_ctl = ioremap(res.start + percpu_offset,
resource_size(&res));
if (!dgt_clk_ctl) {
pr_err("Failed to map DGT control base\n");
return;
}
writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
iounmap(dgt_clk_ctl);
}
if (of_property_read_u32(np, "clock-frequency", &freq)) {
pr_err("Unknown frequency\n");
return;
}
of_node_put(np);
event_base = base + 0x4;
sts_base = base + 0x88;
source_base = cpu0_base + 0x24;
freq /= 4;
writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
msm_timer_init(freq, 32, irq, !!percpu_offset);
}
#endif
static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
u32 sts)
{
event_base = ioremap(event, SZ_64);
if (!event_base) {
pr_err("Failed to map event base\n");
return 1;
}
source_base = ioremap(source, SZ_64);
if (!source_base) {
pr_err("Failed to map source base\n");
return 1;
void __iomem *base;
base = ioremap(addr, SZ_256);
if (!base) {
pr_err("Failed to map timer base\n");
return -ENOMEM;
}
event_base = base + event;
source_base = base + source;
if (sts)
sts_base = base + sts;
return 0;
}
@ -315,7 +307,7 @@ void __init msm7x01_timer_init(void)
{
struct clocksource *cs = &msm_clocksource;
if (msm_timer_map(0xc0100000, 0xc0100010))
if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
return;
cs->read = msm_read_timer_count_shift;
cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
@ -326,14 +318,14 @@ void __init msm7x01_timer_init(void)
void __init msm7x30_timer_init(void)
{
if (msm_timer_map(0xc0100004, 0xc0100024))
if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
return;
msm_timer_init(24576000 / 4, 32, 1, false);
}
void __init qsd8x50_timer_init(void)
{
if (msm_timer_map(0xAC100000, 0xAC100010))
if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
return;
msm_timer_init(19200000 / 4, 32, 7, false);
}