drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk
Factor in clear values wherever required while updating destination
min/max.
References: HSDES#1604444184
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Cc: mesa-dev@lists.freedesktop.org
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180510200708.18097-1-michel.thierry@intel.com
Cc: stable@vger.kernel.org
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180514165445.9198-1-michel.thierry@intel.com
(backported from commit 0c79f9cb77
)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
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@ -7326,6 +7326,9 @@ enum {
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#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
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#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
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#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
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#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
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/* WaCatErrorRejectionIssue */
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#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
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#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
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@ -1149,6 +1149,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
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WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
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GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
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/* WaClearHIZ_WM_CHICKEN3:bxt,glk */
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if (IS_GEN9_LP(dev_priv))
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WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
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/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
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ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
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if (ret)
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