irqchip fixes for Linux 5.7, take #2
- Fix the mbigen driver to properly free its MSI descriptors on teardown - Fix the TI INTA driver to avoid handling spurious interrupts from masked interrupts - Fix the SiFive PLIC driver to use the correct interrupt priority mask - Fix the Amlogic Meson gpio driver creative locking - Fix the GICv4.1 virtual SGI set_affinity callback to update the effective affinity - Allow the GICv4.x driver to synchronize with the HW pending table parsing - Fix a couple of missing static attributes -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAl6ZZBsPHG1hekBrZXJu ZWwub3JnAAoJECPQ0LrRPXpDUkcP/iw7geZx+5A/2hVTAF27SWdq9GNrDCcsRXQy XcV/OVdCsblzpGBsSMgMdmZxB4RRq+w33XNR+7fplwZpHiTyg/51sivhOnDyhrKI jiy0/yvb3JDIEPNouMRggDNtrhpzsJaXu9ENO//W2SBR6lgkFz3Ux1nv1+EF26J+ L0m4anvKkk/kLlbuxRPBC8ADP8h6uEoLESCJ+telIDCY6lKSOh7wTaeRVi24D4jL 4JqQXULMpMhEp8i9DSTqzktHWQo/wuPqVRStqULvAZG7Q2t18hI+OTRHGoyaY3WC Mhz5yh/t+UTJhSzXNGeN2P4EkwCva4LNajd+fe4tlrxi/z6TZzIsonATdQj0fQDe Ju4IjbHkEZxQ9jk1uckBA9jS4NdcT9HOQcnCoWMHIclwD4/GLx+Lq9/l3g7kmRR/ fquptoLMjzRH9GX/W6Uy2e6qRyaPfm9e3d9RrtqiUCMOhSolLYooKKsG4i3zVzKC yggZQeIUrV8+x+xB4VNbUV0pMh6BSUWAD5Kmjky7eM902XPlRotVqTDsOfht2aeU 2NVa1rZ7ElylDZSzYpHVTa6+TISb1phtKhGoXejt6h/Y+cCSaKGKB1mQnJWuLgEz 7uMGB7qohPqV2sWUDxtzVYD6W6OuLsBWcbHyNqin1S5lHzLm8lqUrIEo6URdVhes UGqiwAbI =a+I2 -----END PGP SIGNATURE----- Merge tag 'irqchip-fixes-5.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent Pull irqchip fixes from Marc Zyngier: - Fix the mbigen driver to properly free its MSI descriptors on teardown - Fix the TI INTA driver to avoid handling spurious interrupts from masked interrupts - Fix the SiFive PLIC driver to use the correct interrupt priority mask - Fix the Amlogic Meson gpio driver creative locking - Fix the GICv4.1 virtual SGI set_affinity callback to update the effective affinity - Allow the GICv4.x driver to synchronize with the HW pending table parsing - Fix a couple of missing static attributes
This commit is contained in:
commit
b5963029d9
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@ -416,7 +416,7 @@ static const struct irq_domain_ops bcm7038_l1_domain_ops = {
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.map = bcm7038_l1_map,
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};
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int __init bcm7038_l1_of_init(struct device_node *dn,
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static int __init bcm7038_l1_of_init(struct device_node *dn,
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struct device_node *parent)
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{
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struct bcm7038_l1_chip *intc;
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@ -14,6 +14,7 @@
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#include <linux/dma-iommu.h>
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#include <linux/efi.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/irqdomain.h>
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#include <linux/list.h>
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#include <linux/log2.h>
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@ -3672,6 +3673,20 @@ out:
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return IRQ_SET_MASK_OK_DONE;
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}
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static void its_wait_vpt_parse_complete(void)
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{
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void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
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u64 val;
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if (!gic_rdists->has_vpend_valid_dirty)
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return;
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WARN_ON_ONCE(readq_relaxed_poll_timeout(vlpi_base + GICR_VPENDBASER,
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val,
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!(val & GICR_VPENDBASER_Dirty),
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10, 500));
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}
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static void its_vpe_schedule(struct its_vpe *vpe)
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{
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void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
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@ -3702,6 +3717,8 @@ static void its_vpe_schedule(struct its_vpe *vpe)
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val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
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val |= GICR_VPENDBASER_Valid;
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gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
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its_wait_vpt_parse_complete();
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}
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static void its_vpe_deschedule(struct its_vpe *vpe)
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@ -3910,6 +3927,8 @@ static void its_vpe_4_1_schedule(struct its_vpe *vpe,
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val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);
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gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
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its_wait_vpt_parse_complete();
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}
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static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
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@ -4035,6 +4054,7 @@ static int its_sgi_set_affinity(struct irq_data *d,
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* not on the host (since they can only be targetting a vPE).
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* Tell the kernel we've done whatever it asked for.
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*/
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irq_data_update_effective_affinity(d, mask_val);
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return IRQ_SET_MASK_OK;
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}
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@ -873,6 +873,7 @@ static int __gic_update_rdist_properties(struct redist_region *region,
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gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID);
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gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) |
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gic_data.rdists.has_rvpeid);
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gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY);
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/* Detect non-sensical configurations */
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if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) {
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@ -893,10 +894,11 @@ static void gic_update_rdist_properties(void)
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if (WARN_ON(gic_data.ppi_nr == UINT_MAX))
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gic_data.ppi_nr = 0;
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pr_info("%d PPIs implemented\n", gic_data.ppi_nr);
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pr_info("%sVLPI support, %sdirect LPI support, %sRVPEID support\n",
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!gic_data.rdists.has_vlpis ? "no " : "",
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!gic_data.rdists.has_direct_lpi ? "no " : "",
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!gic_data.rdists.has_rvpeid ? "no " : "");
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if (gic_data.rdists.has_vlpis)
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pr_info("GICv4 features: %s%s%s\n",
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gic_data.rdists.has_direct_lpi ? "DirectLPI " : "",
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gic_data.rdists.has_rvpeid ? "RVPEID " : "",
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gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : "");
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}
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/* Check whether it's single security state view */
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@ -1620,6 +1622,7 @@ static int __init gic_init_bases(void __iomem *dist_base,
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gic_data.rdists.has_rvpeid = true;
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gic_data.rdists.has_vlpis = true;
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gic_data.rdists.has_direct_lpi = true;
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gic_data.rdists.has_vpend_valid_dirty = true;
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if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
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err = -ENOMEM;
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@ -220,10 +220,16 @@ static int mbigen_irq_domain_alloc(struct irq_domain *domain,
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return 0;
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}
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static void mbigen_irq_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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platform_msi_domain_free(domain, virq, nr_irqs);
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}
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static const struct irq_domain_ops mbigen_domain_ops = {
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.translate = mbigen_domain_translate,
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.alloc = mbigen_irq_domain_alloc,
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.free = irq_domain_free_irqs_common,
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.free = mbigen_irq_domain_free,
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};
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static int mbigen_of_create_domain(struct platform_device *pdev,
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@ -144,12 +144,17 @@ struct meson_gpio_irq_controller {
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static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
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unsigned int reg, u32 mask, u32 val)
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{
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unsigned long flags;
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u32 tmp;
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spin_lock_irqsave(&ctl->lock, flags);
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tmp = readl_relaxed(ctl->base + reg);
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tmp &= ~mask;
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tmp |= val;
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writel_relaxed(tmp, ctl->base + reg);
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spin_unlock_irqrestore(&ctl->lock, flags);
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}
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static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl)
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@ -196,14 +201,15 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
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unsigned long hwirq,
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u32 **channel_hwirq)
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{
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unsigned long flags;
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unsigned int idx;
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spin_lock(&ctl->lock);
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spin_lock_irqsave(&ctl->lock, flags);
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/* Find a free channel */
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idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
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if (idx >= NUM_CHANNEL) {
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spin_unlock(&ctl->lock);
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spin_unlock_irqrestore(&ctl->lock, flags);
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pr_err("No channel available\n");
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return -ENOSPC;
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}
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/* Mark the channel as used */
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set_bit(idx, ctl->channel_map);
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spin_unlock_irqrestore(&ctl->lock, flags);
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/*
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* Setup the mux of the channel to route the signal of the pad
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* to the appropriate input of the GIC
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*/
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*channel_hwirq = &(ctl->channel_irqs[idx]);
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spin_unlock(&ctl->lock);
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pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
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hwirq, idx, **channel_hwirq);
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@ -287,13 +293,9 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
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val |= REG_EDGE_POL_LOW(params, idx);
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}
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spin_lock(&ctl->lock);
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meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
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REG_EDGE_POL_MASK(params, idx), val);
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spin_unlock(&ctl->lock);
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return 0;
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}
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@ -66,7 +66,7 @@ struct mvebu_icu_irq_data {
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unsigned int type;
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};
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DEFINE_STATIC_KEY_FALSE(legacy_bindings);
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static DEFINE_STATIC_KEY_FALSE(legacy_bindings);
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static void mvebu_icu_init(struct mvebu_icu *icu,
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struct mvebu_icu_msi_data *msi_data,
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@ -56,7 +56,7 @@
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#define CONTEXT_THRESHOLD 0x00
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#define CONTEXT_CLAIM 0x04
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#define PLIC_DISABLE_THRESHOLD 0xf
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#define PLIC_DISABLE_THRESHOLD 0x7
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#define PLIC_ENABLE_THRESHOLD 0
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struct plic_priv {
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@ -37,6 +37,7 @@
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#define VINT_ENABLE_SET_OFFSET 0x0
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#define VINT_ENABLE_CLR_OFFSET 0x8
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#define VINT_STATUS_OFFSET 0x18
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#define VINT_STATUS_MASKED_OFFSET 0x20
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/**
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* struct ti_sci_inta_event_desc - Description of an event coming to
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chained_irq_enter(irq_desc_get_chip(desc), desc);
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val = readq_relaxed(inta->base + vint_desc->vint_id * 0x1000 +
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VINT_STATUS_OFFSET);
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VINT_STATUS_MASKED_OFFSET);
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for_each_set_bit(bit, &val, MAX_EVENTS_PER_VINT) {
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virq = irq_find_mapping(domain, vint_desc->events[bit].hwirq);
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@ -243,6 +243,7 @@
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#define GICR_TYPER_PLPIS (1U << 0)
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#define GICR_TYPER_VLPIS (1U << 1)
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#define GICR_TYPER_DIRTY (1U << 2)
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#define GICR_TYPER_DirectLPIS (1U << 3)
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#define GICR_TYPER_LAST (1U << 4)
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#define GICR_TYPER_RVPEID (1U << 7)
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@ -686,6 +687,7 @@ struct rdists {
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bool has_vlpis;
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bool has_rvpeid;
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bool has_direct_lpi;
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bool has_vpend_valid_dirty;
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};
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struct irq_domain;
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