MIPS: Octeon: Use device tree to register serial ports.
Switch to using the device tree to register serial ports. Add all the ports with compatible = "cavium,octeon-3860-uart". Octeon serial ports have their own device type, required port flags, and I/O functions, so using of_serial.c is not indicated. We need to do this as late_initcall, as the 8250 driver must be initialized before we add any ports. 8250 initialization is done at device_initcall time. The OCTEON_IRQ_UART{0,1,2} symbols are removed as they are now unused and interfere with irq_domain used by the device tree code. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Cc: linux-mips@linux-mips.org Cc: devicetree-discuss@lists.ozlabs.org Cc: Rob Herring <rob.herring@calxeda.com> Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/3942/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -1184,9 +1184,6 @@ static void __init octeon_irq_init_ciu(void)
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq);
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for (i = 0; i < 4; i++)
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octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq);
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for (i = 0; i < 4; i++)
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@ -1203,7 +1200,6 @@ static void __init octeon_irq_init_ciu(void)
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for (i = 0; i < 16; i++)
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octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq);
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gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio");
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@ -43,95 +43,67 @@ void octeon_serial_out(struct uart_port *up, int offset, int value)
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cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
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}
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/*
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* Allocated in .bss, so it is all zeroed.
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*/
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#define OCTEON_MAX_UARTS 3
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static struct plat_serial8250_port octeon_uart8250_data[OCTEON_MAX_UARTS + 1];
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static struct platform_device octeon_uart8250_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = octeon_uart8250_data,
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static int __devinit octeon_serial_probe(struct platform_device *pdev)
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{
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int irq, res;
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struct resource *res_mem;
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struct uart_port port;
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/* All adaptors have an irq. */
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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memset(&port, 0, sizeof(port));
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port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
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port.type = PORT_OCTEON;
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port.iotype = UPIO_MEM;
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port.regshift = 3;
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port.dev = &pdev->dev;
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if (octeon_is_simulation())
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/* Make simulator output fast*/
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port.uartclk = 115200 * 16;
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else
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port.uartclk = octeon_get_io_clock_rate();
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port.serial_in = octeon_serial_in;
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port.serial_out = octeon_serial_out;
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port.irq = irq;
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res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res_mem == NULL) {
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dev_err(&pdev->dev, "found no memory resource\n");
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return -ENXIO;
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}
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port.mapbase = res_mem->start;
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port.membase = ioremap(res_mem->start, resource_size(res_mem));
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res = serial8250_register_port(&port);
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return res >= 0 ? 0 : res;
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}
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static struct of_device_id octeon_serial_match[] = {
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{
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.compatible = "cavium,octeon-3860-uart",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, octeon_serial_match);
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static struct platform_driver octeon_serial_driver = {
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.probe = octeon_serial_probe,
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.driver = {
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.owner = THIS_MODULE,
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.name = "octeon_serial",
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.of_match_table = octeon_serial_match,
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},
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};
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static void __init octeon_uart_set_common(struct plat_serial8250_port *p)
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{
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p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
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p->type = PORT_OCTEON;
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p->iotype = UPIO_MEM;
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p->regshift = 3; /* I/O addresses are every 8 bytes */
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if (octeon_is_simulation())
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/* Make simulator output fast*/
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p->uartclk = 115200 * 16;
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else
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p->uartclk = octeon_get_io_clock_rate();
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p->serial_in = octeon_serial_in;
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p->serial_out = octeon_serial_out;
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}
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static int __init octeon_serial_init(void)
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{
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int enable_uart0;
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int enable_uart1;
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int enable_uart2;
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struct plat_serial8250_port *p;
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#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
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/*
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* If we are configured to run as the second of two kernels,
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* disable uart0 and enable uart1. Uart0 is owned by the first
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* kernel
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*/
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enable_uart0 = 0;
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enable_uart1 = 1;
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#else
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/*
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* We are configured for the first kernel. We'll enable uart0
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* if the bootloader told us to use 0, otherwise will enable
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* uart 1.
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*/
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enable_uart0 = (octeon_get_boot_uart() == 0);
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enable_uart1 = (octeon_get_boot_uart() == 1);
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#ifdef CONFIG_KGDB
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enable_uart1 = 1;
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#endif
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#endif
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/* Right now CN52XX is the only chip with a third uart */
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enable_uart2 = OCTEON_IS_MODEL(OCTEON_CN52XX);
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p = octeon_uart8250_data;
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if (enable_uart0) {
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/* Add a ttyS device for hardware uart 0 */
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octeon_uart_set_common(p);
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p->membase = (void *) CVMX_MIO_UARTX_RBR(0);
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p->mapbase = CVMX_MIO_UARTX_RBR(0) & ((1ull << 49) - 1);
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p->irq = OCTEON_IRQ_UART0;
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p++;
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}
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if (enable_uart1) {
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/* Add a ttyS device for hardware uart 1 */
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octeon_uart_set_common(p);
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p->membase = (void *) CVMX_MIO_UARTX_RBR(1);
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p->mapbase = CVMX_MIO_UARTX_RBR(1) & ((1ull << 49) - 1);
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p->irq = OCTEON_IRQ_UART1;
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p++;
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}
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if (enable_uart2) {
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/* Add a ttyS device for hardware uart 2 */
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octeon_uart_set_common(p);
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p->membase = (void *) CVMX_MIO_UART2_RBR;
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p->mapbase = CVMX_MIO_UART2_RBR & ((1ull << 49) - 1);
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p->irq = OCTEON_IRQ_UART2;
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p++;
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}
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BUG_ON(p > &octeon_uart8250_data[OCTEON_MAX_UARTS]);
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return platform_device_register(&octeon_uart8250_device);
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return platform_driver_register(&octeon_serial_driver);
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}
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device_initcall(octeon_serial_init);
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late_initcall(octeon_serial_init);
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