drm/i915/perf: fix flex eu registers programming
We were reserving fewer dwords in the ring than necessary. Indeed we're always writing all registers once, so discard the actual number of registers given by the user and just program the whitelisted ones once. Fixes:19f81df285
("drm/i915/perf: Add OA unit support for Gen 8+") Reported-by: Matthew Auld <matthew.william.auld@gmail.com> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Cc: <stable@vger.kernel.org> # v4.12+ Link: https://patchwork.freedesktop.org/patch/msgid/20170803165812.2373-6-lionel.g.landwerlin@intel.com (cherry picked from commit01d928e9a1
) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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@ -1601,11 +1601,11 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req)
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u32 *cs;
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int i;
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cs = intel_ring_begin(req, n_flex_regs * 2 + 4);
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cs = intel_ring_begin(req, ARRAY_SIZE(flex_mmio) * 2 + 4);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = MI_LOAD_REGISTER_IMM(n_flex_regs + 1);
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*cs++ = MI_LOAD_REGISTER_IMM(ARRAY_SIZE(flex_mmio) + 1);
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*cs++ = i915_mmio_reg_offset(GEN8_OACTXCONTROL);
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*cs++ = (dev_priv->perf.oa.period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
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