drm/i915/bxt: Move WaForceEnableNonCoherent to Skylake only
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -951,17 +951,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
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GEN9_ENABLE_YV12_BUGFIX);
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}
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if (INTEL_REVID(dev) <= SKL_REVID_D0) {
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/*
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*Use Force Non-Coherent whenever executing a 3D context. This
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* is a workaround for a possible hang in the unlikely event
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* a TLB invalidation occurs during a PSD flush.
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*/
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/* WaForceEnableNonCoherent:skl */
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WA_SET_BIT_MASKED(HDC_CHICKEN0,
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HDC_FORCE_NON_COHERENT);
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}
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/* Wa4x4STCOptimizationDisable:skl */
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WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
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@ -1039,6 +1028,17 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
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WA_SET_BIT_MASKED(HIZ_CHICKEN,
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BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
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if (INTEL_REVID(dev) <= SKL_REVID_D0) {
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/*
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*Use Force Non-Coherent whenever executing a 3D context. This
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* is a workaround for a possible hang in the unlikely event
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* a TLB invalidation occurs during a PSD flush.
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*/
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/* WaForceEnableNonCoherent:skl */
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WA_SET_BIT_MASKED(HDC_CHICKEN0,
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HDC_FORCE_NON_COHERENT);
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}
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return skl_tune_iz_hashing(ring);
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}
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