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Merge remote-tracking branch 'origin/dts/imx' into dts/next 

* origin/dts/imx: (648 commits)
  LF-261: arm64: dts: imx8mq: Set parent clock for IMX8MQ_CLK_AUDIO_AHB
  LF-235: arm64: dts: imx8qm: disable all hdmi ss modules defaultly
  LF-257-02 dts: imx6ull: change the usdhc root clock to 396MHz
  LF-257-01 ARM: dts: imx6ull/ulz-14x14-evk: update usdhc1 pin group
  LF-270 ARM64: dts: imx8mq.dtsi: set the IMX8MQ_CLK_NAND_USDHC_BUS clock rate
  ...
5.4-rM2-2.2.x-imx-squashed
Dong Aisheng 2019-12-02 18:01:17 +08:00
parent 219d54332a 4798f8f73d
commit b62cc9d2c6
257 changed files with 35295 additions and 865 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

127
Documentation/devicetree/bindings/crypto/fsl-sec4.txt
View File

@ -202,6 +202,26 @@ EXAMPLE
};
=====================================================================
Secure memory (SM) Node
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,imx6q-caam-sm"
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: Specifies a two SM parameters: an offset from
the parent physical address and the length the SM registers.
EXAMPLE
caam_sm: caam-sm@100000 {
compatible = "fsl,imx6q-caam-sm";
reg = <0x100000 0x4000>;
};
=====================================================================
Run Time Integrity Check (RTIC) Node
@ -365,6 +385,79 @@ EXAMPLE
interrupts = <93 2>;
};
=====================================================================
CAAM SNVS Node
Load the SECVIO node.
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,imx6q-caam-snvs".
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical
address and length of the SEC4 configuration
registers.
=====================================================================
Security Violation (SECVIO) Node
Reports security violations.
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,imx6q-caam-secvio".
- interrupts
Usage: required
Value type: <prop_encoded-array>
Definition: Specifies the interrupts generated by this
device. The value of the interrupts property
consists of one interrupt specifier. The format
of the specifier is defined by the binding document
describing the node's interrupt parent.
- jtag-tamper
Usage: optional-but-recommended
Value type: <string>
Definition:
Security tamper on the JTAG
Must include "enabled" to enable.
- watchdog-tamper
Usage: optional-but-recommended
Value type: <string>
Definition:
Security tamper on the watchdog
Must include "enabled" to enable.
- internal-boot-tamper
Usage: optional-but-recommended
Value type: <string>
Definition:
Security tamper on the internal boot
Must include "enabled" to enable.
- external-pin-tamper
Usage: optional-but-recommended
Value type: <string>
Definition:
Security tamper on the external pin
Must include "enabled" to enable.
EXAMPLE
irq_sec_vio: caam_secvio {
compatible = "fsl,imx6q-caam-secvio";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
jtag-tamper = "disabled";
watchdog-tamper = "enabled";
internal-boot-tamper = "enabled";
external-pin-tamper = "disabled";
};
=====================================================================
Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
@ -394,18 +487,14 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
value type: <u32>
Definition: LP register offset. default it is 0x34.
- clocks
Usage: optional, required if SNVS LP RTC requires explicit
enablement of clocks
Value type: <prop_encoded-array>
Definition: a clock specifier describing the clock required for
enabling and disabling SNVS LP RTC.
- clock-names
Usage: optional, required if SNVS LP RTC requires explicit
enablement of clocks
Value type: <string>
Definition: clock name string should be "snvs-rtc".
- clocks
Usage: optional
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the source clock for
snvs register access. If i.MX clk driver defines the clock node,
it needs user to specify the clocks in device tree for all modules
with snvs LP/HP registers access. The modules involved snvs LP/HP
registers access are snvs-power key, snvs-rtc, and caam.
EXAMPLE
sec_mon_rtc_lp@1 {
@ -550,4 +639,18 @@ FULL EXAMPLE
};
};
caam_snvs: caam-snvs@30370000 {
compatible = "fsl,imx6q-caam-snvs";
reg = <0x30370000 0x10000>;
};
irq_sec_vio: caam_secvio {
compatible = "fsl,imx6q-caam-secvio";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
jtag-tamper = "disabled";
watchdog-tamper = "enabled";
internal-boot-tamper = "enabled";
external-pin-tamper = "disabled";
};
=====================================================================

9
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
View File

@ -38,6 +38,15 @@ Optional properties:
The regulator will be enabled when initializing the PCIe host and
disabled either as part of the init process or when shutting down the
host.
- ext_osc: use the external oscillator as ref clock( 1: external OSC is
used, 0 internal PLL is used).
- hard_wired: the PCIe port is hard wired to the EP device(0: one slot
is connected).
- reserved-region: one reserved no-map memory used by PCIe EP/RC
validation system.
- interrupt-names: Optional include the following entries:
- "dma": The interrupt that is asserted when an DMA interrupter
is received
Additional required properties for imx6sx-pcie:
- clock names: Must include the following additional entries:

82
arch/arm/boot/dts/Makefile
View File

@ -435,8 +435,16 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-rex-basic.dtb \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabreauto-enetirq.dtb \
imx6dl-sabreauto-flexcan1.dtb \
imx6dl-sabreauto-ecspi.dtb \
imx6dl-sabreauto-gpmi-weim.dtb \
imx6dl-sabrelite.dtb \
imx6dl-sabresd.dtb \
imx6dl-sabresd-ldo.dtb \
imx6dl-sabresd-btwifi.dtb \
imx6dl-sabresd-hdcp.dtb \
imx6dl-sabresd-enetirq.dtb \
imx6dl-savageboard.dtb \
imx6dl-ts4900.dtb \
imx6dl-ts7970.dtb \
@ -514,8 +522,17 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-pistachio.dtb \
imx6q-rex-pro.dtb \
imx6q-sabreauto.dtb \
imx6q-sabreauto-enetirq.dtb \
imx6q-sabreauto-flexcan1.dtb \
imx6q-sabreauto-ecspi.dtb \
imx6q-sabreauto-gpmi-weim.dtb \
imx6q-sabrelite.dtb \
imx6q-sabresd.dtb \
imx6q-sabresd-ldo.dtb \
imx6q-sabresd-btwifi.dtb \
imx6q-sabresd-hdcp.dtb \
imx6q-sabresd-uart.dtb \
imx6q-sabresd-enetirq.dtb \
imx6q-savageboard.dtb \
imx6q-sbc6x.dtb \
imx6q-tbs2910.dtb \
@ -541,7 +558,13 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6qp-nitrogen6_som2.dtb \
imx6qp-phytec-mira-rdk-nand.dtb \
imx6qp-sabreauto.dtb \
imx6qp-sabreauto-flexcan1.dtb \
imx6qp-sabreauto-ecspi.dtb \
imx6qp-sabreauto-gpmi-weim.dtb \
imx6qp-sabresd.dtb \
imx6qp-sabresd-ldo.dtb \
imx6qp-sabresd-btwifi.dtb \
imx6qp-sabresd-hdcp.dtb \
imx6qp-tx6qp-8037.dtb \
imx6qp-tx6qp-8037-mb7.dtb \
imx6qp-tx6qp-8137.dtb \
@ -550,21 +573,45 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6qp-zii-rdu2.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
imx6sl-evk-ldo.dtb \
imx6sl-evk-csi.dtb \
imx6sl-evk-uart.dtb \
imx6sl-evk-btwifi.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SLL) += \
imx6sll-evk.dtb
imx6sll-evk.dtb \
imx6sll-evk-reva.dtb \
imx6sll-evk-btwifi.dtb
dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-nitrogen6sx.dtb \
imx6sx-sabreauto.dtb \
imx6sx-sdb-reva.dtb \
imx6sx-sdb-reva-ldo.dtb \
imx6sx-sdb-sai.dtb \
imx6sx-sdb.dtb \
imx6sx-sdb-ldo.dtb \
imx6sx-sdb-emmc.dtb \
imx6sx-sdb-lcdif1.dtb \
imx6sx-sdb-m4.dtb \
imx6sx-sdb-mqs.dtb \
imx6sx-sdb-btwifi.dtb \
imx6sx-softing-vining-2000.dtb \
imx6sx-udoo-neo-basic.dtb \
imx6sx-udoo-neo-extended.dtb \
imx6sx-udoo-neo-full.dtb
dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb \
imx6ul-14x14-evk-csi.dtb \
imx6ul-14x14-evk-emmc.dtb \
imx6ul-14x14-evk-btwifi.dtb \
imx6ul-14x14-evk-btwifi-oob.dtb \
imx6ul-14x14-evk-ecspi-slave.dtb \
imx6ul-14x14-evk-ecspi.dtb \
imx6ul-14x14-evk-gpmi-weim.dtb \
imx6ul-9x9-evk.dtb \
imx6ul-9x9-evk-ldo.dtb \
imx6ul-9x9-evk-btwifi.dtb \
imx6ul-9x9-evk-btwifi-oob.dtb \
imx6ul-ccimx6ulsbcexpress.dtb \
imx6ul-ccimx6ulsbcpro.dtb \
imx6ul-geam.dtb \
@ -581,12 +628,23 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-14x14-evk-emmc.dtb \
imx6ull-14x14-evk-btwifi.dtb \
imx6ull-14x14-evk-btwifi-oob.dtb \
imx6ull-14x14-evk-gpmi-weim.dtb \
imx6ull-9x9-evk.dtb \
imx6ull-9x9-evk-ldo.dtb \
imx6ull-9x9-evk-btwifi.dtb \
imx6ull-9x9-evk-btwifi-oob.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ull-phytec-segin-ff-rdk-nand.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-phytec-segin-lc-rdk-nand.dtb \
imx6ulz-14x14-evk.dtb
imx6ulz-14x14-evk.dtb \
imx6ulz-14x14-evk-btwifi.dtb \
imx6ulz-14x14-evk-gpmi-weim.dtb \
imx6ulz-14x14-evk-emmc.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-emmc-eval-v3.dtb \
@ -598,15 +656,33 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-pico-pi.dtb \
imx7d-sbc-imx7.dtb \
imx7d-sdb.dtb \
imx7d-sdb-epdc.dtb \
imx7d-sdb-mipi-dsi.dtb \
imx7d-sdb-gpmi-weim.dtb \
imx7d-sdb-m4.dtb \
imx7d-sdb-qspi.dtb \
imx7d-sdb-reva.dtb \
imx7d-sdb-sht11.dtb \
imx7d-12x12-lpddr3-val.dtb \
imx7d-12x12-lpddr3-val-sai.dtb \
imx7d-zii-rmu2.dtb \
imx7d-zii-rpu2.dtb \
imx7s-colibri-eval-v3.dtb \
imx7s-mba7.dtb \
imx7s-warp.dtb
dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-evk.dtb
imx7ulp-evk.dtb \
imx7ulp-evk-ft5416.dtb \
imx7ulp-evk-mipi.dtb \
imx7ulp-evkb.dtb \
imx7ulp-evkb-emmc.dtb \
imx7ulp-evkb-sd1.dtb \
imx7ulp-evkb-spi-slave.dtb \
imx7ulp-evkb-sensors-to-i2c5.dtb \
imx7ulp-evkb-lpuart.dtb \
imx7ulp-evkb-mipi.dtb \
imx7ulp-evkb-rm68200-wxga.dtb \
imx7ulp-evkb-rm68191-qhd.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
ls1021a-qds.dtb \

36
arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts 100644
View File

@ -0,0 +1,36 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2014 Freescale Semiconductor, Inc.
#include "imx6dl-sabreauto.dts"
&ecspi1 {
pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
status = "okay";
};
&can2 {
/* max7310_c on i2c3 is gone */
status = "disabled";
};
&i2c3 {
/* pin conflict with ecspi1 */
status = "disabled";
};
&uart3 {
/* the uart3 depends on the i2c3, so disable it too. */
status = "disabled";
};
&usbh1 {
/* max7310_b on i2c3 is gone */
status = "disabled";
};
&usbotg {
dr_mode = "peripheral";
status = "okay";
};

16
arch/arm/boot/dts/imx6dl-sabreauto-enetirq.dts 100644
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2013 Freescale Semiconductor, Inc.
// Copyright 2019 NXP
#include "imx6dl-sabreauto.dts"
&fec {
pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>;
};
&mlb {
status = "disabled";
};

18
arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts 100644
View File

@ -0,0 +1,18 @@
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6dl-sabreauto.dts"
&can1{
status = "okay";
};
&fec {
/* pin conflict with flexcan1 */
status = "disabled";
};

45
arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts 100644
View File

@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2014 Freescale Semiconductor, Inc.
#include "imx6dl-sabreauto.dts"
&ecspi1 {
/* pin conflict with weim */
status = "disabled";
};
&can2 {
/* max7310_c on i2c3 is gone */
status = "disabled";
};
&gpmi {
status = "okay";
};
&i2c3 {
/* pin conflict with weim */
status = "disabled";
};
&uart3 {
/* pin conflict with gpmi and weim */
status = "disabled";
};
&usbh1 {
/* max7310_b on i2c3 is gone */
status = "disabled";
};
&usbotg {
dr_mode = "peripheral";
status = "okay";
};
&weim {
pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
status = "okay";
};

18
arch/arm/boot/dts/imx6dl-sabreauto.dts
View File

@ -26,3 +26,21 @@
396000 1175000
>;
};
&ldb {
lvds-channel@0 {
crtc = "ipu1-di0";
};
lvds-channel@1 {
crtc = "ipu1-di1";
};
};
&mxcfb1 {
status = "okay";
};
&mxcfb2 {
status = "okay";
};

11
arch/arm/boot/dts/imx6dl-sabresd-btwifi.dts 100644
View File

@ -0,0 +1,11 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6dl-sabresd.dts"
#include "imx6qdl-sabresd-btwifi.dtsi"

15
arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts 100644
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2014 Freescale Semiconductor, Inc.
// Copyright 2019 NXP
#include "imx6dl-sabresd.dts"
&fec {
pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>;
interrupts-extended = <&gpio1 6 0x4>, <&gpc 0 119 0x4>;
};
&i2c3 {
status = "disabled";
};

36
arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts 100644
View File

@ -0,0 +1,36 @@
/*
* Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6dl-sabresd.dts"
&gpc {
/* use ldo-enable, u-boot will check it and configure */
fsl,ldo-bypass = <0>;
};
&hdmi_video {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_hdcp>;
fsl,hdcp;
};
&i2c2 {
status = "disable";
};
&reg_arm {
/delete-property/ vin-supply;
};
&reg_pu {
/delete-property/ vin-supply;
};
&reg_soc {
/delete-property/ vin-supply;
};

34
arch/arm/boot/dts/imx6dl-sabresd-ldo.dts 100644
View File

@ -0,0 +1,34 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6dl-sabresd.dts"
&gpc {
/* use ldo-enable, u-boot will check it and configure */
fsl,ldo-bypass = <0>;
};
&reg_arm {
/delete-property/ vin-supply;
};
&reg_pu {
/delete-property/ vin-supply;
};
&reg_soc {
/delete-property/ vin-supply;
};
&wdog1 {
status = "okay";
};
&wdog2 {
status = "disabled";
};

156
arch/arm/boot/dts/imx6dl-sabresd.dts
View File

@ -12,7 +12,163 @@
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
};
&battery {
offset-charger = <1485>;
offset-discharger = <1464>;
offset-usb-charger = <1285>;
};
&iomuxc {
epdc {
pinctrl_epdc_elan_touch: epdc_elan_touch_grp {
fsl,pins = <
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x80000000
MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x80000000
MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000
>;
};
pinctrl_epdc_0: epdcgrp-0 {
fsl,pins = <
MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x80000000
MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x80000000
MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x80000000
MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x80000000
MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x80000000
MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x80000000
MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x80000000
MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x80000000
MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x80000000
MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x80000000
MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x80000000
MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x80000000
MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000
MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x80000000
MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x80000000
MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000
MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x80000000
MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000
MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000
MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000
>;
};
};
};
&epdc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_epdc_0>;
V3P3-supply = <&V3P3_reg>;
VCOM-supply = <&VCOM_reg>;
DISPLAY-supply = <&DISPLAY_reg>;
status = "okay";
};
&i2c3 {
elan@10 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_epdc_elan_touch>;
compatible = "elan,elan-touch";
reg = <0x10>;
interrupt-parent = <&gpio3>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
gpio_elan_cs = <&gpio2 18 0>;
gpio_elan_rst = <&gpio3 8 0>;
gpio_intr = <&gpio3 28 0>;
status = "okay";
};
max17135@48 {
compatible = "maxim,max17135";
reg = <0x48>;
vneg_pwrup = <1>;
gvee_pwrup = <1>;
vpos_pwrup = <2>;
gvdd_pwrup = <1>;
gvdd_pwrdn = <1>;
vpos_pwrdn = <2>;
gvee_pwrdn = <1>;
vneg_pwrdn = <1>;
SENSOR-supply = <&reg_sensors>;
gpio_pmic_pwrgood = <&gpio2 21 0>;
gpio_pmic_vcom_ctrl = <&gpio3 17 0>;
gpio_pmic_wakeup = <&gpio3 20 0>;
gpio_pmic_v3p3 = <&gpio2 20 0>;
gpio_pmic_intr = <&gpio2 25 0>;
regulators {
DISPLAY_reg: DISPLAY {
regulator-name = "DISPLAY";
};
GVDD_reg: GVDD {
/* 20v */
regulator-name = "GVDD";
};
GVEE_reg: GVEE {
/* -22v */
regulator-name = "GVEE";
};
HVINN_reg: HVINN {
/* -22v */
regulator-name = "HVINN";
};
HVINP_reg: HVINP {
/* 20v */
regulator-name = "HVINP";
};
VCOM_reg: VCOM {
regulator-name = "VCOM";
/* Real max: -500000 */
regulator-max-microvolt = <4325000>;
/* Real min: -4325000 */
regulator-min-microvolt = <500000>;
};
VNEG_reg: VNEG {
/* -15v */
regulator-name = "VNEG";
};
VPOS_reg: VPOS {
/* 15v */
regulator-name = "VPOS";
};
V3P3_reg: V3P3 {
regulator-name = "V3P3";
};
};
};
};
&ipu1_csi1_from_ipu1_csi1_mux {
clock-lanes = <0>;
data-lanes = <1 2>;
};
&ldb {
lvds-channel@0 {
crtc = "ipu1-di0";
};
lvds-channel@1 {
crtc = "ipu1-di1";
};
};
&mxcfb1 {
status = "okay";
};
&mxcfb2 {
status = "okay";
};
&pxp {
status = "okay";
};

88
arch/arm/boot/dts/imx6dl.dtsi 100644 → 100755
View File

@ -38,9 +38,13 @@
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
<&clks IMX6QDL_CLK_PLL1_SYS>,
<&clks IMX6QDL_CLK_PLL1>,
<&clks IMX6QDL_PLL1_BYPASS>,
<&clks IMX6QDL_PLL1_BYPASS_SRC>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
"pll1_sw", "pll1_sys", "pll1",
"pll1_bypass", "pll1_bypass_src";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
@ -77,26 +81,73 @@
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x14000000>;
linux,cma-default;
};
};
soc {
ocram: sram@900000 {
ocram: sram@905000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
reg = <0x905000 0x1B000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
ocram_optee: sram@918000 {
compatible = "fsl,optee-lpm-sram";
reg = <0x918000 0x8000>;
overw_reg = <&ocram 0x905000 0x13000>;
};
gpu: gpu@00130000 {
compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
<0x10000000 0x0>, <0x0 0x8000000>;
reg-names = "iobase_3d", "iobase_2d",
"phys_baseaddr", "contiguous_mem";
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
<0 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_3d", "irq_2d";
clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>,
<&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_DUMMY>;
clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
"gpu2d_clk", "gpu3d_clk",
"gpu3d_shader_clk";
resets = <&src 0>, <&src 3>;
reset-names = "gpu3d", "gpu2d";
power-domains = <&pd_pu>;
};
aips1: aips-bus@2000000 {
iomuxc: iomuxc@20e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
pxp: pxp@20f0000 {
reg = <0x020f0000 0x4000>;
compatible = "fsl,imx6dl-pxp-dma";
reg = <0x20f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_DUMMY>;
clock-names = "pxp-axi", "disp-axi";
status = "disabled";
};
epdc: epdc@20f4000 {
reg = <0x020f4000 0x4000>;
compatible = "fsl,imx6dl-epdc";
reg = <0x20f4000 0x4000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI1>;
clock-names = "epdc_axi", "epdc_pix";
};
};
@ -124,6 +175,12 @@
};
};
&dcic2 {
clocks = <&clks IMX6QDL_CLK_DCIC1 >,
<&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/
clock-names = "dcic", "disp-axi";
};
&gpio1 {
gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
<&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
@ -302,12 +359,19 @@
};
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb";
clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
clock-names = "di0_pll", "di1_pll",
<&clks IMX6QDL_CLK_IPU2_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
<&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
<&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
clock-names = "ldb_di0", "ldb_di1",
"di0_sel", "di1_sel",
"di0", "di1";
"di2_sel",
"ldb_di0_div_3_5", "ldb_di1_div_3_5",
"ldb_di0_div_7", "ldb_di1_div_7",
"ldb_di0_div_sel", "ldb_di1_div_sel";
};
&mipi_csi {
@ -389,3 +453,7 @@
&vpu {
compatible = "fsl,imx6dl-vpu", "cnm,coda960";
};
&vpu_fsl {
iramsize = <0>;
};

36
arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts 100644
View File

@ -0,0 +1,36 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2014 Freescale Semiconductor, Inc.
#include "imx6q-sabreauto.dts"
&ecspi1 {
pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
status = "okay";
};
&can2 {
/* max7310_c on i2c3 is gone */
status = "disabled";
};
&i2c3 {
/* pin conflict with ecspi1 */
status = "disabled";
};
&uart3 {
/* the uart3 depends on the i2c3, so disable it too. */
status = "disabled";
};
&usbh1 {
/* max7310_b on i2c3 is gone */
status = "disabled";
};
&usbotg {
/* max7310_c on i2c3 is gone */
status = "okay";
dr_mode = "peripheral";
};

15
arch/arm/boot/dts/imx6q-sabreauto-enetirq.dts 100644
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2019 NXP
#include "imx6q-sabreauto.dts"
&fec {
pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>;
};
&mlb {
status = "disabled";
};

18
arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts 100644
View File

@ -0,0 +1,18 @@
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6q-sabreauto.dts"
&can1{
status = "okay";
};
&fec {
/* pin conflict with flexcan1 */
status = "disabled";
};

46
arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts 100644
View File

@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2014 Freescale Semiconductor, Inc.
#include "imx6q-sabreauto.dts"
&ecspi1 {
/* pin conflict with weim */
status = "disabled";
};
&can2 {
/* max7310_c on i2c3 is gone */
status = "disabled";
};
&gpmi {
status = "okay";
};
&i2c3 {
/* pin conflict with weim */
status = "disabled";
};
&uart3 {
/* pin conflict with gpmi and weim */
status = "disabled";
};
&usbh1 {
/* max7310_b on i2c3 is gone */
status = "disabled";
};
&usbotg {
/* max7310_c on i2c3 is gone */
status = "okay";
dr_mode = "peripheral";
};
&weim {
pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
status = "okay";
};

25
arch/arm/boot/dts/imx6q-sabreauto.dts
View File

@ -13,6 +13,31 @@
compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
};
&ldb {
lvds-channel@0 {
crtc = "ipu2-di0";
};
lvds-channel@1 {
crtc = "ipu2-di1";
};
};
&mxcfb1 {
status = "okay";
};
&mxcfb2 {
status = "okay";
};
&mxcfb3 {
status = "okay";
};
&mxcfb4 {
status = "okay";
};
&sata {
status = "okay";
};

11
arch/arm/boot/dts/imx6q-sabresd-btwifi.dts 100644
View File

@ -0,0 +1,11 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6q-sabresd.dts"
#include "imx6qdl-sabresd-btwifi.dtsi"

15
arch/arm/boot/dts/imx6q-sabresd-enetirq.dts 100644
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2014 Freescale Semiconductor, Inc.
// Copyright 2019 NXP
#include "imx6q-sabresd.dts"
&fec {
pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>;
interrupts-extended = <&gpio1 6 0x4>, <&gpc 0 119 0x4>;
};
&i2c3 {
status = "disabled";
};

40
arch/arm/boot/dts/imx6q-sabresd-hdcp.dts 100644
View File

@ -0,0 +1,40 @@
/*
* Copyright 2012-2014 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx6q-sabresd.dts"
&gpc {
/* use ldo-enable, u-boot will check it and configure */
fsl,ldo-bypass = <0>;
};
&hdmi_video {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_hdcp>;
fsl,hdcp;
};
&i2c2 {
status = "disable";
};
&reg_arm {
/delete-property/ vin-supply;
};
&reg_pu {
/delete-property/ vin-supply;
};
&reg_soc {
/delete-property/ vin-supply;
};

34
arch/arm/boot/dts/imx6q-sabresd-ldo.dts 100644
View File

@ -0,0 +1,34 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6q-sabresd.dts"
&gpc {
/* use ldo-enable, u-boot will check it and configure */
fsl,ldo-bypass = <0>;
};
&reg_arm {
/delete-property/ vin-supply;
};
&reg_pu {
/delete-property/ vin-supply;
};
&reg_soc {
/delete-property/ vin-supply;
};
&wdog1 {
status = "okay";
};
&wdog2 {
status = "disabled";
};

23
arch/arm/boot/dts/imx6q-sabresd-uart.dts 100644
View File

@ -0,0 +1,23 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6q-sabresd.dts"
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5_1>;
fsl,uart-has-rtscts;
status = "okay";
/* for DTE mode, add below change */
/* fsl,dte-mode; */
/* pinctrl-0 = <&pinctrl_uart5dte_1>; */
};
&ecspi1 {
status = "disabled";
};

32
arch/arm/boot/dts/imx6q-sabresd.dts
View File

@ -13,6 +13,38 @@
compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
};
&battery {
offset-charger = <1900>;
offset-discharger = <1694>;
offset-usb-charger = <1685>;
};
&ldb {
lvds-channel@0 {
crtc = "ipu2-di0";
};
lvds-channel@1 {
crtc = "ipu2-di1";
};
};
&mxcfb1 {
status = "okay";
};
&mxcfb2 {
status = "okay";
};
&mxcfb3 {
status = "okay";
};
&mxcfb4 {
status = "okay";
};
&sata {
status = "okay";
};

97
arch/arm/boot/dts/imx6q.dtsi
View File

@ -43,9 +43,13 @@
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
<&clks IMX6QDL_CLK_PLL1_SYS>,
<&clks IMX6QDL_CLK_PLL1>,
<&clks IMX6QDL_PLL1_BYPASS>,
<&clks IMX6QDL_PLL1_BYPASS_SRC>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
"pll1_sw", "pll1_sys", "pll1",
"pll1_bypass", "pll1_bypass_src";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
@ -154,13 +158,44 @@
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x14000000>;
linux,cma-default;
};
};
soc {
ocram: sram@900000 {
busfreq: busfreq {
compatible = "fsl,imx_busfreq";
clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
<&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>;
clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg",
"periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc";
interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>;
interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
fsl,max_ddr_freq = <528000000>;
};
ocram: sram@905000 {
compatible = "mmio-sram";
reg = <0x00900000 0x40000>;
reg = <0x905000 0x3B000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
ocram_optee: sram@938000 {
compatible = "fsl,optee-lpm-sram";
reg = <0x938000 0x8000>;
overw_reg = <&ocram 0x905000 0x33000>;
};
aips-bus@2000000 { /* AIPS1 */
spba-bus@2000000 {
ecspi5: spi@2018000 {
@ -172,7 +207,7 @@
clocks = <&clks IMX6Q_CLK_ECSPI5>,
<&clks IMX6Q_CLK_ECSPI5>;
clock-names = "ipg", "per";
dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -203,6 +238,30 @@
clock-names = "bus", "core";
power-domains = <&pd_pu>;
#cooling-cells = <2>;
status = "disabled";
};
gpu: gpu@00130000 {
compatible = "fsl,imx6q-gpu";
reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
<0x02204000 0x4000>, <0x10000000 0x0>,
<0x0 0x8000000>;
reg-names = "iobase_3d", "iobase_2d",
"iobase_vg", "phys_baseaddr",
"contiguous_mem";
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
<0 10 IRQ_TYPE_LEVEL_HIGH>,
<0 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_3d", "irq_2d", "irq_vg";
clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>,
<&clks IMX6QDL_CLK_GPU3D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>;
clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
"gpu3d_axi_clk", "gpu2d_clk",
"gpu3d_clk", "gpu3d_shader_clk";
resets = <&src 0>, <&src 3>, <&src 3>;
reset-names = "gpu3d", "gpu2d", "gpuvg";
power-domains = <&pd_pu>;
};
ipu2: ipu@2800000 {
@ -214,9 +273,17 @@
<0 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_IPU2>,
<&clks IMX6QDL_CLK_IPU2_DI0>,
<&clks IMX6QDL_CLK_IPU2_DI1>;
clock-names = "bus", "di0", "di1";
<&clks IMX6QDL_CLK_IPU2_DI1>,
<&clks IMX6QDL_CLK_IPU2_DI0_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0>,
<&clks IMX6QDL_CLK_LDB_DI1>;
clock-names = "bus",
"di0", "di1",
"di0_sel", "di1_sel",
"ldb_di0", "ldb_di1";
resets = <&src 4>;
bypass_reset = <0>;
ipu2_csi0: port@0 {
reg = <0>;
@ -429,13 +496,19 @@
};
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel", "di2_sel", "di3_sel",
"di0", "di1";
<&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
<&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
<&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
clock-names = "ldb_di0", "ldb_di1",
"di0_sel", "di1_sel",
"di2_sel", "di3_sel",
"ldb_di0_div_3_5", "ldb_di1_div_3_5",
"ldb_di0_div_7", "ldb_di1_div_7",
"ldb_di0_div_sel", "ldb_di1_div_sel";
lvds-channel@0 {
port@2 {

379
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
View File

@ -11,7 +11,14 @@
stdout-path = &uart4;
};
memory@10000000 {
aliases {
mxcfb0 = &mxcfb1;
mxcfb1 = &mxcfb2;
mxcfb2 = &mxcfb3;
mxcfb3 = &mxcfb4;
};
memory: memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x80000000>;
};
@ -84,6 +91,14 @@
regulator-always-on;
};
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
@ -121,26 +136,113 @@
vin-supply = <&reg_can_en>;
};
reg_si4763_vio1: regulator@3 {
compatible = "regulator-fixed";
regulator-name = "vio1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_si4763_vio2: regulator@4 {
compatible = "regulator-fixed";
regulator-name = "vio2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_si4763_vd: regulator@5 {
compatible = "regulator-fixed";
regulator-name = "vd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_si4763_va: regulator@6 {
compatible = "regulator-fixed";
regulator-name = "va";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_hdmi: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "hdmi-5v-supply";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
hdmi-5v-supply = <&swbst_reg>;
};
mxcfb1: fb@0 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "ldb";
interface_pix_fmt = "RGB666";
default_bpp = <16>;
int_clk = <0>;
late_init = <0>;
status = "disabled";
};
mxcfb2: fb@1 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "hdmi";
interface_pix_fmt = "RGB24";
mode_str ="1920x1080M@60";
default_bpp = <24>;
int_clk = <0>;
late_init = <0>;
status = "disabled";
};
mxcfb3: fb@2 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "lcd";
interface_pix_fmt = "RGB565";
mode_str ="CLAA-WVGA";
default_bpp = <16>;
int_clk = <0>;
late_init = <0>;
status = "disabled";
};
mxcfb4: fb@3 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "ldb";
interface_pix_fmt = "RGB666";
default_bpp = <16>;
int_clk = <0>;
late_init = <0>;
status = "disabled";
};
sound-cs42888 {
compatible = "fsl,imx6-sabreauto-cs42888",
"fsl,imx-audio-cs42888";
"fsl,imx-audio-cs42888";
model = "imx-cs42888";
audio-cpu = <&esai>;
audio-asrc = <&asrc>;
esai-controller = <&esai>;
asrc-controller = <&asrc>;
audio-codec = <&codec>;
audio-routing =
"Line Out Jack", "AOUT1L",
"Line Out Jack", "AOUT1R",
"Line Out Jack", "AOUT2L",
"Line Out Jack", "AOUT2R",
"Line Out Jack", "AOUT3L",
"Line Out Jack", "AOUT3R",
"Line Out Jack", "AOUT4L",
"Line Out Jack", "AOUT4R",
"AIN1L", "Line In Jack",
"AIN1R", "Line In Jack",
"AIN2L", "Line In Jack",
"AIN2R", "Line In Jack";
};
sound-hdmi {
compatible = "fsl,imx6q-audio-hdmi",
"fsl,imx-audio-hdmi";
model = "imx-audio-hdmi";
hdmi-controller = <&hdmi_audio>;
};
sound-fm {
compatible = "fsl,imx-audio-si476x",
"fsl,imx-tuner-si476x";
model = "imx-radio-si4763";
ssi-controller = <&ssi2>;
fm-controller = <&si476x_codec>;
mux-int-port = <2>;
mux-ext-port = <5>;
};
sound-spdif {
@ -174,19 +276,22 @@
#size-cells = <0>;
reg = <1>;
adv7180: camera@21 {
compatible = "adi,adv7180";
adv7180: adv7180@21 {
compatible = "adv,adv7180";
reg = <0x21>;
powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio1>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
port {
adv7180_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <8>;
};
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_1>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "csi_mclk";
DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */
AVDD-supply = <&reg_3p3v>; /* 1.8v */
DVDD-supply = <&reg_3p3v>; /* 1.8v */
PVDD-supply = <&reg_3p3v>; /* 1.8v */
pwn-gpios = <&max7310_b 2 0>;
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
cvbs = <1>;
};
max7310_a: gpio@30 {
@ -214,8 +319,9 @@
};
light-sensor@44 {
compatible = "isil,isl29023";
compatible = "fsl,isl29023";
reg = <0x44>;
rext = <499>;
interrupt-parent = <&gpio5>;
interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
};
@ -237,6 +343,25 @@
};
};
};
v4l2_cap_0 {
compatible = "fsl,imx6q-v4l2-capture";
ipu_id = <0>;
csi_id = <0>;
mclk_source = <0>;
status = "okay";
};
v4l2_out {
compatible = "fsl,mxc_v4l2_output";
status = "okay";
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&ipu1_csi0_from_ipu1_csi0_mux {
@ -244,7 +369,10 @@
};
&ipu1_csi0_mux_from_parallel_sensor {
/* Downstream driver doesn't use endpoints */
/*
remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
*/
bus-width = <8>;
};
@ -261,11 +389,23 @@
<&clks IMX6QDL_CLK_PLL4_POST_DIV>;
assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
<&clks IMX6QDL_PLL4_BYPASS_SRC>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
};
&dcic1 {
dcic_id = <0>;
dcic_mux = "dcic-hdmi";
status = "okay";
};
&dcic2 {
dcic_id = <1>;
dcic_mux = "dcic-lvds0";
status = "okay";
};
&ecspi1 {
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
@ -295,8 +435,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,magic-packet;
fsl,err006687-workaround-present;
status = "okay";
};
@ -304,6 +443,7 @@
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */
xceiver-supply = <&reg_can_stby>;
status = "disabled"; /* pin conflict with fec */
};
@ -318,13 +458,30 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
/* enable at -gpmi-weim.dts due to pin conflict */
status = "disabled";
};
&hdmi_audio {
status = "okay";
};
&hdmi {
&hdmi_cec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_cec>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&hdmi_core {
ipu_id = <0>;
disp_id = <1>;
status = "okay";
};
&hdmi_video {
fsl,phy_reg_vlev = <0x294>;
fsl,phy_reg_cksymtx = <0x800d>;
HDMI-supply = <&reg_hdmi>;
status = "okay";
};
@ -453,6 +610,25 @@
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
};
si4763: si4763@63 {
compatible = "si4761";
reg = <0x63>;
va-supply = <&reg_si4763_va>;
vd-supply = <&reg_si4763_vd>;
vio1-supply = <&reg_si4763_vio1>;
vio2-supply = <&reg_si4763_vio2>;
revision-a10; /* set to default A10 compatible command set */
si476x_codec: si476x-codec {
compatible = "si476x-codec";
};
};
hdmi_edid: edid@50 {
compatible = "fsl,imx6-hdmi-i2c";
reg = <0x50>;
};
};
&i2c3 {
@ -474,6 +650,14 @@
>;
};
pinctrl_audmux: audmux {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
@ -511,6 +695,12 @@
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_enet_irq: enetirqgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
@ -595,6 +785,30 @@
>;
};
pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */
fsl,pins = <
MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
@ -636,6 +850,14 @@
>;
};
pinctrl_mlb: mlb {
fsl,pins = <
MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000
MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000
MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000
>;
};
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
@ -660,6 +882,24 @@
>;
};
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
>;
};
pinctrl_uart3dte_1: uart3dtegrp-1 {
fsl,pins = <
MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
@ -673,6 +913,17 @@
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
@ -780,6 +1031,7 @@
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
primary;
status = "okay";
display-timings {
@ -797,6 +1049,33 @@
};
};
};
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing1>;
timing1: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&mlb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mlb>;
status = "okay";
};
&pwm3 {
@ -815,6 +1094,26 @@
status = "okay";
};
&ssi2 {
assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>;
fsl,mode = "i2s-master";
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */
<&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */
fsl,uart-has-rtscts;
status = "okay";
/* for DTE mode, add below change */
/* fsl,dte-mode; */
/* pinctrl-0 = <&pinctrl_uart3dte_1>; */
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
@ -833,6 +1132,14 @@
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
no-1-8-v;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;

104
arch/arm/boot/dts/imx6qdl-sabresd-btwifi.dtsi 100644
View File

@ -0,0 +1,104 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* NOTE: This DTS file is wrote for plugging in Murata 1MW M.2
* into SD2 slot by using Murata uSD-to-M.2 Adapter.
*
* By default, OOB IRQ is enabled with below HW rework.
* HW rework:
* Install R209,R210,R211,R212,R213,R214,R215 on SDB board.
*/
/ {
leds {
compatible = "gpio-leds";
status = "disabled";
};
modem_reset: modem-reset {
compatible = "gpio-reset";
reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
#reset-cells = <0>;
};
usdhc1_pwrseq: usdhc1_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
};
};
&ecspi1 {
status = "disabled";
};
&iomuxc {
imx6qdl-sabresd-murata-v2 {
pinctrl_btreg: btreggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
/* add MUXing entry for SD2 4-bit interface and configure control pins */
pinctrl_wifi: wifigrp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x13069 /* WL_REG_ON */
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0b001 /* WL_HOST_WAKE */
>;
};
};
};
&pinctrl_gpio_leds {
fsl,pins = <
>;
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5_1
&pinctrl_btreg>;
fsl,uart-has-rtscts;
resets = <&modem_reset>;
status = "okay";
/* for DTE mode, add below change */
/* fsl,dte-mode; */
/* pinctrl-0 = <&pinctrl_uart5dte_1>; */
};
&usdhc2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi>;
bus-width = <4>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
mmc-pwrseq = <&usdhc1_pwrseq>;
pm-ignore-notify;
cap-power-off-card;
/delete-property/ enable-sdio-wakeup;
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio4>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};

370
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View File

@ -8,11 +8,31 @@
#include <dt-bindings/input/input.h>
/ {
aliases {
mxcfb0 = &mxcfb1;
mxcfb1 = &mxcfb2;
mxcfb2 = &mxcfb3;
mxcfb3 = &mxcfb4;
};
chosen {
stdout-path = &uart1;
};
memory@10000000 {
battery: max8903@0 {
compatible = "fsl,max8903-charger";
pinctrl-names = "default";
dok_input = <&gpio2 24 1>;
uok_input = <&gpio1 27 1>;
chg_input = <&gpio3 23 1>;
flt_input = <&gpio5 2 1>;
fsl,dcm_always_high;
fsl,dc_valid;
fsl,usb_valid;
status = "okay";
};
memory: memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
@ -66,6 +86,15 @@
enable-active-high;
};
reg_hdmi: regulator-hdmi {
compatible = "regulator-fixed";
regulator-name = "hdmi-5v-supply";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
hdmi-5v-supply = <&swbst_reg>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@ -97,17 +126,86 @@
compatible = "fsl,imx6q-sabresd-wm8962",
"fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-cpu = <&ssi2>;
audio-codec = <&codec>;
asrc-controller = <&asrc>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
"IN3R", "AMIC",
"DMIC", "MICBIAS",
"DMICDAT", "DMIC",
"CPU-Playback", "ASRC-Playback",
"Playback", "CPU-Playback",
"ASRC-Capture", "CPU-Capture",
"CPU-Capture", "Capture";
mux-int-port = <2>;
mux-ext-port = <3>;
codec-master;
hp-det-gpios = <&gpio7 8 1>;
mic-det-gpios = <&gpio1 9 1>;
};
sound-hdmi {
compatible = "fsl,imx6q-audio-hdmi",
"fsl,imx-audio-hdmi";
model = "imx-audio-hdmi";
hdmi-controller = <&hdmi_audio>;
};
mxcfb1: fb@0 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "ldb";
interface_pix_fmt = "RGB666";
default_bpp = <16>;
int_clk = <0>;
late_init = <0>;
status = "disabled";
};
mxcfb2: fb@1 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "hdmi";
interface_pix_fmt = "RGB24";
mode_str ="1920x1080M@60";
default_bpp = <24>;
int_clk = <0>;
late_init = <0>;
status = "disabled";
};
mxcfb3: fb@2 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "lcd";
interface_pix_fmt = "RGB565";
mode_str ="CLAA-WVGA";
default_bpp = <16>;
int_clk = <0>;
late_init = <0>;
status = "disabled";
};
mxcfb4: fb@3 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "ldb";
interface_pix_fmt = "RGB666";
default_bpp = <16>;
int_clk = <0>;
late_init = <0>;
status = "disabled";
};
lcd@0 {
compatible = "fsl,lcd";
ipu_id = <0>;
disp_id = <0>;
default_ifmt = "RGB565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1>;
status = "okay";
};
backlight_lvds: backlight-lvds {
@ -123,21 +221,33 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
red {
charger-led {
gpios = <&gpio1 2 0>;
default-state = "on";
linux,default-trigger = "max8903-charger-charging";
retain-state-suspended;
default-state = "off";
};
};
panel {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
v4l2_cap_0 {
compatible = "fsl,imx6q-v4l2-capture";
ipu_id = <0>;
csi_id = <0>;
mclk_source = <0>;
status = "okay";
};
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
v4l2_cap_1 {
compatible = "fsl,imx6q-v4l2-capture";
ipu_id = <0>;
csi_id = <1>;
mclk_source = <0>;
status = "okay";
};
v4l2_out {
compatible = "fsl,mxc_v4l2_output";
status = "okay";
};
};
@ -149,7 +259,9 @@
};
&ipu1_csi0_mux_from_parallel_sensor {
#if 0
remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
#endif
};
&ipu1_csi0 {
@ -160,6 +272,11 @@
&mipi_csi {
status = "okay";
ipu_id = <0>;
csi_id = <1>;
v_channel = <0>;
lanes = <2>;
#if 0
port@0 {
reg = <0>;
@ -169,6 +286,7 @@
data-lanes = <1 2>;
};
};
#endif
};
&audmux {
@ -180,8 +298,20 @@
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
};
&dcic1 {
dcic_id = <0>;
dcic_mux = "dcic-hdmi";
status = "okay";
};
&dcic2 {
dcic_id = <1>;
dcic_mux = "dcic-lvds1";
status = "okay";
};
&ecspi1 {
@ -204,13 +334,34 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
fsl,magic-packet;
status = "okay";
};
&hdmi {
&gpc {
fsl,ldo-bypass = <1>;
};
&hdmi_audio {
status = "okay";
};
&hdmi_cec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_cec>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&hdmi_core {
ipu_id = <0>;
disp_id = <0>;
status = "okay";
};
&hdmi_video {
fsl,phy_reg_vlev = <0x294>;
fsl,phy_reg_cksymtx = <0x800d>;
HDMI-supply = <&reg_hdmi>;
status = "okay";
};
@ -253,6 +404,7 @@
vddio-supply = <&reg_sensors>;
};
#if 0
ov5642: camera@3c {
compatible = "ovti,ov5642";
pinctrl-names = "default";
@ -277,6 +429,23 @@
};
};
};
#endif
ov564x: ov564x@3c {
compatible = "ovti,ov564x";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_2>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "csi_mclk";
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3, on rev B board is VGEN5 */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */
rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
};
};
&i2c2 {
@ -295,6 +464,15 @@
wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
};
max11801@48 {
compatible = "maxim,max11801";
reg = <0x48>;
interrupt-parent = <&gpio3>;
interrupts = <26 2>;
work-mode = <1>;/*DCM mode*/
};
#if 0
ov5640: camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
@ -317,6 +495,22 @@
};
};
};
#endif
ov564x_mipi: ov564x_mipi@3c { /* i2c2 driver */
compatible = "ovti,ov564x_mipi";
reg = <0x3c>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "csi_mclk";
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
AVDD-supply = <&vgen3_reg>; /* 2.8v rev C board is VGEN3 rev B board is VGEN5 */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */
rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */
csi_id = <1>;
mclk = <24000000>;
mclk_source = <0>;
};
pmic: pfuze100@8 {
compatible = "fsl,pfuze100";
@ -418,6 +612,11 @@
};
};
};
hdmi_edid: edid@50 {
compatible = "fsl,imx6-hdmi-i2c";
reg = <0x50>;
};
};
&i2c3 {
@ -446,13 +645,14 @@
};
light-sensor@44 {
compatible = "isil,isl29023";
compatible = "fsl,isl29023";
reg = <0x44>;
rext = <499>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_isl29023_int>;
interrupt-parent = <&gpio3>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
vcc-supply = <&reg_sensors>;
vdd-supply = <&reg_sensors>;
};
};
@ -472,6 +672,12 @@
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
>;
};
@ -514,6 +720,12 @@
>;
};
pinctrl_enet_irq: enetirqgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
@ -524,7 +736,14 @@
pinctrl_hdmi_cec: hdmicecgrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0
>;
};
pinctrl_hdmi_hdcp: hdmihdcpgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
>;
};
@ -573,6 +792,59 @@
>;
};
pinctrl_ipu1: ipu1grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
@ -634,6 +906,24 @@
>;
};
pinctrl_uart5_1: uart5grp-1 {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1
MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1
>;
};
pinctrl_uart5dte_1: uart5dtegrp-1 {
fsl,pins = <
MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1
MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
@ -704,16 +994,45 @@
&ldb {
status = "okay";
lvds-channel@1 {
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
port@4 {
reg = <4>;
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
primary;
status = "okay";
display-timings {
native-mode = <&timing1>;
timing1: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
@ -812,6 +1131,7 @@
bus-width = <8>;
non-removable;
no-1-8-v;
auto-cmd23-broken;
status = "okay";
};

149
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -156,6 +156,11 @@
interrupt-parent = <&gpc>;
ranges;
caam_sm: caam-sm@100000 {
compatible = "fsl,imx6q-caam-sm";
reg = <0x100000 0x4000>;
};
dma_apbh: dma-apbh@110000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x00110000 0x2000>;
@ -215,6 +220,45 @@
};
};
hdmi_core: hdmi_core@120000 {
compatible = "fsl,imx6q-hdmi-core";
reg = <0x120000 0x9000>;
clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
<&clks IMX6QDL_CLK_HDMI_IAHB>,
<&clks IMX6QDL_CLK_HSI_TX>;
clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
status = "disabled";
};
hdmi_video: hdmi_video@20e0000 {
compatible = "fsl,imx6q-hdmi-video";
reg = <0x20e0000 0x1000>;
reg-names = "hdmi_gpr";
interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
<&clks IMX6QDL_CLK_HDMI_IAHB>,
<&clks IMX6QDL_CLK_HSI_TX>;
clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
status = "disabled";
};
hdmi_audio: hdmi_audio@120000 {
compatible = "fsl,imx6q-hdmi-audio";
clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
<&clks IMX6QDL_CLK_HDMI_IAHB>,
<&clks IMX6QDL_CLK_HSI_TX>;
clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
dmas = <&sdma 2 26 0>;
dma-names = "tx";
status = "disabled";
};
hdmi_cec: hdmi_cec@120000 {
compatible = "fsl,imx6q-hdmi-cec";
interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
gpu_3d: gpu@130000 {
compatible = "vivante,gc";
reg = <0x00130000 0x4000>;
@ -225,6 +269,7 @@
clock-names = "bus", "core", "shader";
power-domains = <&pd_pu>;
#cooling-cells = <2>;
status = "disabled";
};
gpu_2d: gpu@134000 {
@ -236,6 +281,19 @@
clock-names = "bus", "core";
power-domains = <&pd_pu>;
#cooling-cells = <2>;
status = "disabled";
};
ocrams: sram@00900000 {
compatible = "fsl,lpm-sram";
reg = <0x00900000 0x4000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
ocrams_ddr: sram@00904000 {
compatible = "fsl,ddr-lpm-sram";
reg = <0x00904000 0x1000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
timer@a00600 {
@ -318,7 +376,7 @@
clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
<&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
<&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
<&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
clock-names = "core", "rxtx0",
"rxtx1", "rxtx2",
@ -337,7 +395,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI1>,
<&clks IMX6QDL_CLK_ECSPI1>;
clock-names = "ipg", "per";
dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -351,7 +409,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI2>,
<&clks IMX6QDL_CLK_ECSPI2>;
clock-names = "ipg", "per";
dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -365,7 +423,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI3>,
<&clks IMX6QDL_CLK_ECSPI3>;
clock-names = "ipg", "per";
dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -379,7 +437,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI4>,
<&clks IMX6QDL_CLK_ECSPI4>;
clock-names = "ipg", "per";
dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -502,6 +560,24 @@
power-domains = <&pd_pu>;
resets = <&src 1>;
iram = <&ocram>;
status = "disabled";
};
vpu_fsl: vpu_fsl@2040000 {
compatible = "fsl,imx6-vpu";
reg = <0x2040000 0x3c000>;
reg-names = "vpu_regs";
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
<0 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq";
clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
<&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
<&clks IMX6QDL_CLK_OCRAM>;
clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
iramsize = <0x21000>;
iram = <&ocram>;
resets = <&src 1>;
power-domains = <&pd_pu>;
};
aipstz@207c000 { /* AIPSTZ1 */
@ -759,6 +835,7 @@
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
regulator-allow-bypass;
};
reg_pu: regulator-vddpu {
@ -776,6 +853,7 @@
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
regulator-allow-bypass;
};
reg_soc: regulator-vddsoc {
@ -793,6 +871,7 @@
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
regulator-allow-bypass;
};
};
@ -812,6 +891,20 @@
fsl,anatop = <&anatop>;
};
irq_sec_vio: caam_secvio {
compatible = "fsl,imx6q-caam-secvio";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
jtag-tamper = "disabled";
watchdog-tamper = "enabled";
internal-boot-tamper = "enabled";
external-pin-tamper = "disabled";
};
caam_snvs: caam-snvs@20cc000 {
compatible = "fsl,imx6q-caam-snvs";
reg = <0x20cc000 0x4000>;
};
snvs: snvs@20cc000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x020cc000 0x4000>;
@ -914,13 +1007,23 @@
};
dcic1: dcic@20e4000 {
reg = <0x020e4000 0x4000>;
compatible = "fsl,imx6q-dcic";
reg = <0x20e4000 0x4000>;
interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>;
clock-names = "dcic", "disp-axi";
gpr = <&gpr>;
status = "disabled";
};
dcic2: dcic@20e8000 {
reg = <0x020e8000 0x4000>;
compatible = "fsl,imx6q-dcic";
reg = <0x20e8000 0x4000>;
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>;
clock-names = "dcic", "disp-axi";
gpr = <&gpr>;
status = "disabled";
};
sdma: sdma@20ec000 {
@ -1046,14 +1149,21 @@
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp";
stop-mode = <&gpr 0x34 27>;
fsl,wakeup_irq = <0>;
status = "disabled";
};
mlb@218c000 {
mlb: mlb@218c000 {
compatible = "fsl,imx6q-mlb150";
reg = <0x0218c000 0x4000>;
interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
<0 117 IRQ_TYPE_LEVEL_HIGH>,
<0 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_MLB>;
clock-names = "mlb";
iram = <&ocram>;
status = "disabled";
};
usdhc1: usdhc@2190000 {
@ -1138,6 +1248,11 @@
reg = <0x021ac000 0x4000>;
};
mmdc0-1@021b0000 { /* MMDC0-1 */
compatible = "fsl,imx6q-mmdc-combine";
reg = <0x021b0000 0x8000>;
};
mmdc0: memory-controller@21b0000 { /* MMDC0 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
@ -1184,15 +1299,15 @@
};
mipi_csi: mipi@21dc000 {
compatible = "fsl,imx6-mipi-csi2";
compatible = "fsl,imx6q-mipi-csi2";
reg = <0x021dc000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 100 0x04>, <0 101 0x04>;
clocks = <&clks IMX6QDL_CLK_HSI_TX>,
<&clks IMX6QDL_CLK_VIDEO_27M>,
<&clks IMX6QDL_CLK_EIM_PODF>;
clock-names = "dphy", "ref", "pix";
<&clks IMX6QDL_CLK_EIM_SEL>;
clock-names = "dphy_clk", "cfg_clk", "pixel_clk";
status = "disabled";
};
@ -1227,6 +1342,7 @@
reg = <0x021e4000 0x4000>;
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_VDOA>;
iram = <&ocram>;
};
uart2: serial@21e8000 {
@ -1286,10 +1402,15 @@
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
<0 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_IPU1>,
<&clks IMX6QDL_CLK_IPU1_DI0>,
<&clks IMX6QDL_CLK_IPU1_DI1>;
clock-names = "bus", "di0", "di1";
<&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
clock-names = "bus",
"di0", "di1",
"di0_sel", "di1_sel",
"ldb_di0", "ldb_di1";
resets = <&src 2>;
bypass_reset = <0>;
ipu1_csi0: port@0 {
reg = <0>;

37
arch/arm/boot/dts/imx6qp-sabreauto-ecspi.dts 100644
View File

@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2015 Freescale Semiconductor, Inc.
#include "imx6qp-sabreauto.dts"
&ecspi1 {
pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
status = "okay";
};
&can2 {
/* max7310_c on i2c3 is gone */
status = "disabled";
};
&i2c3 {
/* pin conflict with ecspi1 */
status = "disabled";
};
&uart3 {
/* the uart3 depends on the i2c3, so disable it too. */
status = "disabled";
};
&usbh1 {
/* max7310_b on i2c3 is gone */
status = "disabled";
};
&usbotg {
/* max7310_c on i2c3 is gone */
status = "okay";
dr_mode = "peripheral";
};

18
arch/arm/boot/dts/imx6qp-sabreauto-flexcan1.dts 100644
View File

@ -0,0 +1,18 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6qp-sabreauto.dts"
&can1{
status = "okay";
};
&fec {
/* pin conflict with flexcan1 */
status = "disabled";
};

46
arch/arm/boot/dts/imx6qp-sabreauto-gpmi-weim.dts 100644
View File

@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2015 Freescale Semiconductor, Inc.
#include "imx6qp-sabreauto.dts"
&ecspi1 {
/* pin conflict with weim */
status = "disabled";
};
&can2 {
/* max7310_c on i2c3 is gone */
status = "disabled";
};
&gpmi {
compatible = "fsl,imx6qp-gpmi-nand";
status = "okay";
};
&i2c3 {
/* pin conflict with weim */
status = "disabled";
};
&uart3 {
/* pin conflict with gpmi and weim */
status = "disabled";
};
&usbh1 {
/* max7310_b on i2c3 is gone */
status = "disabled";
};
&usbotg {
/* max7310_c on i2c3 is gone */
status = "okay";
dr_mode = "peripheral";
};
&weim {
pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
status = "okay";
};

81
arch/arm/boot/dts/imx6qp-sabreauto.dts
View File

@ -12,6 +12,62 @@
compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
};
&pre1 {
status = "okay";
};
&pre2 {
status = "okay";
};
&pre3 {
status = "okay";
};
&pre4 {
status = "okay";
};
&prg1 {
memory-region = <&memory>;
status = "okay";
};
&prg2 {
memory-region = <&memory>;
status = "okay";
};
&mxcfb1 {
prefetch;
status = "okay";
};
&mxcfb2 {
prefetch;
status = "okay";
};
&mxcfb3 {
prefetch;
status = "okay";
};
&mxcfb4 {
prefetch;
status = "okay";
};
&ldb {
lvds-channel@0 {
crtc = "ipu2-di0";
};
lvds-channel@1 {
crtc = "ipu2-di1";
};
};
&i2c2 {
max7322: gpio@68 {
compatible = "maxim,max7322";
@ -21,31 +77,6 @@
};
};
&iomuxc {
imx6qdl-sabreauto {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
};
};
&pcie {
status = "disabled";
};

11
arch/arm/boot/dts/imx6qp-sabresd-btwifi.dts 100644
View File

@ -0,0 +1,11 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6qp-sabresd.dts"
#include "imx6qdl-sabresd-btwifi.dtsi"

39
arch/arm/boot/dts/imx6qp-sabresd-hdcp.dts 100644
View File

@ -0,0 +1,39 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx6qp-sabresd.dts"
&gpc {
/* use ldo-enable, u-boot will check it and configure */
fsl,ldo-bypass = <0>;
};
&hdmi_video {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_hdcp>;
fsl,hdcp;
};
&i2c2 {
status = "disable";
};
&reg_arm {
/delete-property/ vin-supply;
};
&reg_pu {
/delete-property/ vin-supply;
};
&reg_soc {
/delete-property/ vin-supply;
};

42
arch/arm/boot/dts/imx6qp-sabresd-ldo.dts 100644
View File

@ -0,0 +1,42 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6qp-sabresd.dts"
&wdog1 {
status = "okay";
};
&wdog2 {
status = "disabled";
};
&gpc {
/* use ldo-enable, u-boot will check it and configure */
fsl,ldo-bypass = <0>;
};
&reg_arm {
/delete-property/ vin-supply;
};
&reg_pu {
/delete-property/ vin-supply;
};
&reg_soc {
/delete-property/ vin-supply;
};
&wdog1 {
status = "okay";
};
&wdog2 {
status = "disabled";
};

74
arch/arm/boot/dts/imx6qp-sabresd.dts
View File

@ -50,6 +50,76 @@
};
};
&pcie {
status = "disabled";
&ov564x {
AVDD-supply = <&vgen6_reg>; /* 2.8v */
DOVDD-supply = <&sw4_reg>; /* 1.8v */
};
&ov564x_mipi {
AVDD-supply = <&vgen6_reg>; /* 2.8v */
DOVDD-supply = <&sw4_reg>; /* 1.8v */
};
&pcie {
status = "okay";
};
&sata {
status = "okay";
};
&pre1 {
status = "okay";
};
&pre2 {
status = "okay";
};
&pre3 {
status = "okay";
};
&pre4 {
status = "okay";
};
&prg1 {
memory-region = <&memory>;
status = "okay";
};
&prg2 {
memory-region = <&memory>;
status = "okay";
};
&mxcfb1 {
prefetch;
status = "okay";
};
&mxcfb2 {
prefetch;
status = "okay";
};
&mxcfb3 {
prefetch;
status = "okay";
};
&mxcfb4 {
prefetch;
status = "okay";
};
&ldb {
lvds-channel@0 {
crtc = "ipu2-di0";
};
lvds-channel@1 {
crtc = "ipu2-di1";
};
};

69
arch/arm/boot/dts/imx6qp.dtsi
View File

@ -5,6 +5,15 @@
#include "imx6q.dtsi"
/ {
aliases {
pre0 = &pre1;
pre1 = &pre2;
pre2 = &pre3;
pre3 = &pre4;
prg0 = &prg1;
prg1 = &prg2;
};
soc {
ocram2: sram@940000 {
compatible = "mmio-sram";
@ -20,57 +29,63 @@
aips-bus@2100000 {
pre1: pre@21c8000 {
compatible = "fsl,imx6qp-pre";
compatible = "fsl,imx6q-pre";
reg = <0x021c8000 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6QDL_CLK_PRE0>;
clock-names = "axi";
fsl,iram = <&ocram2>;
ocram = <&ocram2>;
status = "disabled";
};
pre2: pre@21c9000 {
compatible = "fsl,imx6qp-pre";
compatible = "fsl,imx6q-pre";
reg = <0x021c9000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6QDL_CLK_PRE1>;
clock-names = "axi";
fsl,iram = <&ocram2>;
ocram = <&ocram2>;
status = "disabled";
};
pre3: pre@21ca000 {
compatible = "fsl,imx6qp-pre";
compatible = "fsl,imx6q-pre";
reg = <0x021ca000 0x1000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6QDL_CLK_PRE2>;
clock-names = "axi";
fsl,iram = <&ocram3>;
ocram = <&ocram3>;
status = "disabled";
};
pre4: pre@21cb000 {
compatible = "fsl,imx6qp-pre";
compatible = "fsl,imx6q-pre";
reg = <0x021cb000 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6QDL_CLK_PRE3>;
clock-names = "axi";
fsl,iram = <&ocram3>;
ocram = <&ocram3>;
status = "disabled";
};
prg1: prg@21cc000 {
compatible = "fsl,imx6qp-prg";
compatible = "fsl,imx6q-prg";
reg = <0x021cc000 0x1000>;
clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
<&clks IMX6QDL_CLK_PRG0_AXI>;
clock-names = "ipg", "axi";
fsl,pres = <&pre1>, <&pre2>, <&pre3>;
clock-names = "apb", "axi";
gpr = <&gpr>;
status = "disabled";
};
prg2: prg@21cd000 {
compatible = "fsl,imx6qp-prg";
compatible = "fsl,imx6q-prg";
reg = <0x021cd000 0x1000>;
clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
<&clks IMX6QDL_CLK_PRG1_AXI>;
clock-names = "ipg", "axi";
fsl,pres = <&pre4>, <&pre2>, <&pre3>;
clock-names = "apb", "axi";
gpr = <&gpr>;
status = "disabled";
};
};
};
@ -88,22 +103,34 @@
&ipu1 {
compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
clocks = <&clks IMX6QDL_CLK_IPU1>,
<&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>,
<&clks IMX6QDL_CLK_PRG0_APB>;
clock-names = "bus",
"di0", "di1",
"di0_sel", "di1_sel",
"ldb_di0", "ldb_di1", "prg";
fsl,prg = <&prg1>;
};
&ipu2 {
compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
clocks = <&clks IMX6QDL_CLK_IPU2>,
<&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>,
<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>,
<&clks IMX6QDL_CLK_PRG1_APB>;
clock-names = "bus",
"di0", "di1",
"di0_sel", "di1_sel",
"ldb_di0", "ldb_di1", "prg";
fsl,prg = <&prg2>;
};
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel", "di2_sel", "di3_sel",
"di0", "di1";
compatible = "fsl,imx6qp-ldb", "fsl,imx6q-ldb", "fsl,imx53-ldb";
};
&mmdc0 {

101
arch/arm/boot/dts/imx6sl-evk-btwifi.dts 100644
View File

@ -0,0 +1,101 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* NOTE: This DTS file is written for plugging in Murata Wi-Fi/BT EVK into SD1
* slot using Murata i.MX InterConnect Ver 1.0 Adapter AND wiring in control
* signals with SD Card Extender on SD3 slot.
* Bluetooth UART connect via SD1 EMMC/MMC Plus pinout.
* WL_REG_ON/BT_REG_ON/WL_HOST_WAKE are connected from SD Card Extender on SD3
* slot.
*/
#include "imx6sl-evk.dts"
/ {
modem_reset: modem-reset {
compatible = "gpio-reset";
reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
#reset-cells = <0>;
};
usdhc1_pwrseq: usdhc1_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio5 16 GPIO_ACTIVE_LOW>;
};
};
&iomuxc {
imx6sl-evk-murata-v1_sdext {
/* Only MUX SD1_DAT0..3 lines so UART4 can be MUXed on higher data lines. */
pinctrl_btreg: btreggrp {
fsl,pins = <
MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x13069 /* BT_REG_ON */
>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <
MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x13069 /* WL_HOST_WAKE */
MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x13069 /* WL_REG_ON */
>;
};
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
>;
};
};
};
/* Murata: declare UART4 interface for Bluetooth. */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_1
&pinctrl_btreg>;
fsl,uart-has-rtscts;
resets = <&modem_reset>;
status = "okay";
/* for DTE mode, add below change */
/* fsl,dte-mode; */
/* pinctrl-0 = <&pinctrl_uart4dte_1>; */
};
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi>;
bus-width = <4>;
no-1-8-v;
non-removable;
mmc-pwrseq = <&usdhc1_pwrseq>;
pm-ignore-notify;
cap-power-off-card;
/delete-property/ enable-sdio-wakeup;
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
bus-width = <1>;
no-1-8-v;
};

17
arch/arm/boot/dts/imx6sl-evk-csi.dts 100644
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
//
//Copyright (C) 2013 Freescale Semiconductor, Inc.
#include "imx6sl-evk.dts"
&csi {
status = "okay";
};
&i2c3 {
status = "okay";
};
&epdc {
status = "disabled";
};

26
arch/arm/boot/dts/imx6sl-evk-ldo.dts 100644
View File

@ -0,0 +1,26 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6sl-evk.dts"
&gpc {
/* use ldo-enable, u-boot will check it and configure */
fsl,ldo-bypass = <0>;
};
&reg_arm {
/delete-property/ vin-supply;
};
&reg_pu {
/delete-property/ vin-supply;
};
&reg_soc {
/delete-property/ vin-supply;
};

23
arch/arm/boot/dts/imx6sl-evk-uart.dts 100644
View File

@ -0,0 +1,23 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6sl-evk.dts"
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_1>;
fsl,uart-has-rtscts;
status = "okay";
/* for DTE mode, add below change */
/* fsl,dte-mode; */
/* pinctrl-0 = <&pinctrl_uart4dte_1>; */
};
&usdhc1 {
status = "disabled";
};

257
arch/arm/boot/dts/imx6sl-evk.dts
View File

@ -12,6 +12,19 @@
model = "Freescale i.MX6 SoloLite EVK Board";
compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
battery: max8903@0 {
compatible = "fsl,max8903-charger";
pinctrl-names = "default";
dok_input = <&gpio4 13 1>;
uok_input = <&gpio4 13 1>;
chg_input = <&gpio4 15 1>;
flt_input = <&gpio4 14 1>;
fsl,dcm_always_high;
fsl,dc_valid;
fsl,adc_disable;
status = "okay";
};
chosen {
stdout-path = &uart1;
};
@ -21,6 +34,19 @@
reg = <0x80000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x14000000>;
linux,cma-default;
};
};
backlight_display: backlight_display {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
@ -40,6 +66,11 @@
};
};
pxp_v4l2_out {
compatible = "fsl,imx6sl-pxp-v4l2";
status = "okay";
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
@ -95,7 +126,7 @@
sound {
compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-cpu = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
@ -106,6 +137,8 @@
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
codec-master;
hp-det-gpios = <&gpio4 19 1>;
};
panel {
@ -128,6 +161,14 @@
status = "okay";
};
&csi {
port {
csi_ep: endpoint {
remote-endpoint = <&ov5640_ep>;
};
};
};
&ecspi1 {
cs-gpios = <&gpio4 11 0>;
pinctrl-names = "default";
@ -143,6 +184,15 @@
};
};
&epdc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_epdc_0>;
V3P3-supply = <&V3P3_reg>;
VCOM-supply = <&VCOM_reg>;
DISPLAY-supply = <&DISPLAY_reg>;
status = "okay";
};
&fec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec>;
@ -151,6 +201,10 @@
status = "okay";
};
&gpc {
fsl,ldo-bypass = <1>;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@ -257,6 +311,89 @@
};
};
};
elan@10 {
compatible = "elan,elan-touch";
reg = <0x10>;
interrupt-parent = <&gpio2>;
interrupts = <10 2>;
gpio_elan_cs = <&gpio2 9 0>;
gpio_elan_rst = <&gpio4 4 0>;
gpio_intr = <&gpio2 10 0>;
status = "okay";
};
ma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
max17135@48 {
compatible = "maxim,max17135";
reg = <0x48>;
vneg_pwrup = <1>;
gvee_pwrup = <2>;
vpos_pwrup = <10>;
gvdd_pwrup = <12>;
gvdd_pwrdn = <1>;
vpos_pwrdn = <2>;
gvee_pwrdn = <8>;
vneg_pwrdn = <10>;
gpio_pmic_pwrgood = <&gpio2 13 0>;
gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
gpio_pmic_wakeup = <&gpio2 14 0>;
gpio_pmic_v3p3 = <&gpio2 7 0>;
gpio_pmic_intr = <&gpio2 12 0>;
regulators {
DISPLAY_reg: DISPLAY {
regulator-name = "DISPLAY";
};
GVDD_reg: GVDD {
/* 20v */
regulator-name = "GVDD";
};
GVEE_reg: GVEE {
/* -22v */
regulator-name = "GVEE";
};
HVINN_reg: HVINN {
/* -22v */
regulator-name = "HVINN";
};
HVINP_reg: HVINP {
/* 20v */
regulator-name = "HVINP";
};
VCOM_reg: VCOM {
regulator-name = "VCOM";
/* Real max value: -500000 */
regulator-max-microvolt = <4325000>;
/* Real min value: -4325000 */
regulator-min-microvolt = <500000>;
};
VNEG_reg: VNEG {
/* -15v */
regulator-name = "VNEG";
};
VPOS_reg: VPOS {
/* 15v */
regulator-name = "VPOS";
};
V3P3_reg: V3P3 {
regulator-name = "V3P3";
};
};
};
};
&i2c2 {
@ -280,6 +417,34 @@
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "disabled";
ov5640: ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi_0>;
clocks = <&clks IMX6SL_CLK_CSI>;
clock-names = "csi_mclk";
AVDD-supply = <&vgen6_reg>; /* 2.8v */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
pwn-gpios = <&gpio1 25 1>;
rst-gpios = <&gpio1 26 0>;
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
port {
ov5640_ep: endpoint {
remote-endpoint = <&csi_ep>;
};
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
@ -295,6 +460,13 @@
MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x17000
MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000
MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x110b0
MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0
>;
};
@ -316,6 +488,39 @@
>;
};
pinctrl_epdc_0: epdcgrp-0 {
fsl,pins = <
MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x80000000
MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x80000000
MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x80000000
MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x80000000
MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x80000000
MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x80000000
MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x80000000
MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x80000000
MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x80000000
MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x80000000
MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000
MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000
MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000
MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000
MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000
MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000
MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000
MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x80000000
MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x80000000
MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x80000000
MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000
MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x80000000
MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x80000000
MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000
MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x80000000
MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000
MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000
MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
@ -358,6 +563,13 @@
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1
MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
@ -427,6 +639,24 @@
>;
};
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x1b0b1
MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x1b0b1
MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x1b0b1
MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x1b0b1
>;
};
pinctrl_uart4dte_1: uart4dtegrp-1 {
fsl,pins = <
MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x1b0b1
MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x1b0b1
MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x1b0b1
MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
@ -543,9 +773,34 @@
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
>;
};
pinctrl_csi_0: csigrp-0 {
fsl,pins = <
MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x110b0
MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0
MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x110b0
MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x110b0
MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0
MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0
MX6SL_PAD_EPDC_D7__CSI_DATA07 0x110b0
MX6SL_PAD_EPDC_D6__CSI_DATA06 0x110b0
MX6SL_PAD_EPDC_D5__CSI_DATA05 0x110b0
MX6SL_PAD_EPDC_D4__CSI_DATA04 0x110b0
MX6SL_PAD_EPDC_D3__CSI_DATA03 0x110b0
MX6SL_PAD_EPDC_D2__CSI_DATA02 0x110b0
MX6SL_PAD_EPDC_D1__CSI_DATA01 0x110b0
MX6SL_PAD_EPDC_D0__CSI_DATA00 0x110b0
MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000
>;
};
};
};
&pxp {
status = "okay";
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp>;

83
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -66,11 +66,17 @@
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
<&clks IMX6SL_CLK_PLL1_SYS>;
clocks = <&clks IMX6SL_CLK_ARM>,
<&clks IMX6SL_CLK_PLL2_PFD2>,
<&clks IMX6SL_CLK_STEP>,
<&clks IMX6SL_CLK_PLL1_SW>,
<&clks IMX6SL_CLK_PLL1_SYS>,
<&clks IMX6SL_CLK_PLL1>,
<&clks IMX6SL_PLL1_BYPASS>,
<&clks IMX6SL_PLL1_BYPASS_SRC>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
"pll1_sw", "pll1_sys", "pll1", "pll1_bypass",
"pll1_bypass_src";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
@ -118,12 +124,51 @@
interrupt-parent = <&gpc>;
ranges;
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
busfreq { /* BUSFREQ */
compatible = "fsl,imx_busfreq";
clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>,
<&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>,
<&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>,
<&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2_PODF>,
<&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>,
<&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>,
<&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM_PODF>,
<&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>,
<&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>,
<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>,
<&clks IMX6SL_CLK_PLL2>, <&clks IMX6SL_CLK_PLL1>, <&clks IMX6SL_PLL1_BYPASS>,
<&clks IMX6SL_PLL1_BYPASS_SRC>;
clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
"periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb",
"ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src",
"pll2_bypass", "pll2", "pll1", "pll1_bypass", "pll1_bypass_src";
fsl,max_ddr_freq = <400000000>;
};
ocrams: sram@900000 {
compatible = "fsl,lpm-sram";
reg = <0x900000 0x4000>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
ocrams_ddr: sram@904000 {
compatible = "fsl,ddr-lpm-sram";
reg = <0x904000 0x1000>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
ocram: sram@905000 {
compatible = "mmio-sram";
reg = <0x905000 0x1B000>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
ocram_optee: sram@918000 {
compatible = "fsl,optee-lpm-sram";
reg = <0x918000 0x8000>;
overw_reg = <&ocram 0x905000 0x13000>;
};
intc: interrupt-controller@a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
@ -591,6 +636,7 @@
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
regulator-allow-bypass;
};
reg_pu: regulator-vddpu {
@ -607,6 +653,7 @@
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
regulator-allow-bypass;
};
reg_soc: regulator-vddsoc {
@ -624,6 +671,7 @@
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
regulator-allow-bypass;
};
};
@ -734,8 +782,14 @@
};
csi: csi@20e4000 {
reg = <0x020e4000 0x4000>;
compatible = "fsl,imx6sl-csi";
reg = <0x20e4000 0x4000>;
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_DUMMY>,
<&clks IMX6SL_CLK_DUMMY>,
<&clks IMX6SL_CLK_DUMMY>;
clock-names = "disp-axi", "csi_mclk", "disp_dcic";
status = "disabled";
};
spdc: spdc@20e8000 {
@ -756,13 +810,20 @@
};
pxp: pxp@20f0000 {
reg = <0x020f0000 0x4000>;
compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
reg = <0x20f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_PXP_AXI>, <&clks IMX6SL_CLK_DUMMY>;
clock-names = "pxp-axi", "disp-axi";
status = "disabled";
};
epdc: epdc@20f4000 {
reg = <0x020f4000 0x4000>;
compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc";
reg = <0x20f4000 0x4000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_EPDC_AXI>, <&clks IMX6SL_CLK_EPDC_PIX>;
clock-names = "epdc_axi", "epdc_pix";
};
lcdif: lcdif@20f8000 {
@ -936,8 +997,10 @@
};
rngb: rngb@21b4000 {
compatible = "fsl,imx25-rngb";
reg = <0x021b4000 0x4000>;
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_DUMMY>;
};
weim: weim@21b8000 {

101
arch/arm/boot/dts/imx6sll-evk-btwifi.dts 100644
View File

@ -0,0 +1,101 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* NOTE: This DTS file is wrote for plugging in Murata 1MW M.2
* into SD3 slot by using Murata uSD-to-M.2 Adapter.
*
* By default, OOB IRQ is not enabled since i.MX6SLL EVK board needs to rework.
* How to enable OOB IRQ ?
* HW rework:
* Install R127 on i.MX6SLL EVK board.
* SW change: add below pin for WL_HOST_WAKE
* pinctrl_wifi: wifigrp {
* fsl,pins = <
* ...
* MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x0b001
* >;
* };
* brcmf: bcrmf@1 {
* reg = <1>;
* compatible = "brcm,bcm4329-fmac";
* interrupt-parent = <&gpio3>;
* interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
* interrupt-names = "host-wake";
* };
*/
#include "imx6sll-evk.dts"
/ {
modem_reset: modem-reset {
compatible = "gpio-reset";
reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
#reset-cells = <0>;
};
usdhc1_pwrseq: usdhc1_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
};
};
&iomuxc {
pinctrl_wifi: wifigrp {
fsl,pins = <
MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130b9
MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9
MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9
MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9
MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9
MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x17059 /* WL_REG_ON */
MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x0b001
>;
};
};
&lcdif {
status = "disabled";
};
&reg_sd3_vmmc {
regulator-always-on;
};
&uart5 {
resets = <&modem_reset>;
status = "okay";
};
&usdhc3 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi>;
bus-width = <4>;
no-1-8-v;
non-removable;
mmc-pwrseq = <&usdhc1_pwrseq>;
pm-ignore-notify;
cap-power-off-card;
/delete-property/ cd-gpios;
/delete-property/ vmmc-supply;
/delete-property/ enable-sdio-wakeup;
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};

15
arch/arm/boot/dts/imx6sll-evk-reva.dts 100644
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2019 NXP.
*
*/
/dts-v1/;
#include "imx6sll-evk.dts"
&usdhc2 {
compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
};

355
arch/arm/boot/dts/imx6sll-evk.dts
View File

@ -24,6 +24,19 @@
reg = <0x80000000 0x80000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x14000000>;
linux,cma-default;
};
};
backlight_display: backlight-display {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
@ -44,6 +57,11 @@
};
};
pxp_v4l2_out {
compatible = "fsl,imx6sl-pxp-v4l2";
status = "okay";
};
reg_usb_otg1_vbus: regulator-otg1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -106,9 +124,18 @@
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
reg_sd2_vmmc: regulator-sd2-vmmc {
compatible = "regulator-fixed";
regulator-name = "eMMC-VCCQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
reg_sd3_vmmc: regulator-sd3-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -117,28 +144,53 @@
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
panel {
compatible = "sii,43wvf1g";
backlight = <&backlight_display>;
dvdd-supply = <&reg_lcd_3v3>;
avdd-supply = <&reg_lcd_5v>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
sound {
compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
model = "wm8962-audio";
audio-cpu = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
codec-master;
hp-det-gpios = <&gpio4 24 1>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux3>;
status = "okay";
};
&cpu0 {
arm-supply = <&sw1a_reg>;
soc-supply = <&sw1c_reg>;
};
&epdc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_epdc0>;
V3P3-supply = <&V3P3_reg>;
VCOM-supply = <&VCOM_reg>;
DISPLAY-supply = <&DISPLAY_reg>;
status = "okay";
};
&gpc {
fsl,ldo-bypass = <1>;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@ -245,6 +297,98 @@
};
};
};
max17135: max17135@48 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_max17135>;
compatible = "maxim,max17135";
reg = <0x48>;
status = "okay";
vneg_pwrup = <1>;
gvee_pwrup = <2>;
vpos_pwrup = <10>;
gvdd_pwrup = <12>;
gvdd_pwrdn = <1>;
vpos_pwrdn = <2>;
gvee_pwrdn = <8>;
vneg_pwrdn = <10>;
gpio_pmic_pwrgood = <&gpio2 13 0>;
gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
gpio_pmic_wakeup = <&gpio2 14 0>;
gpio_pmic_v3p3 = <&gpio2 7 0>;
gpio_pmic_intr = <&gpio2 12 0>;
regulators {
DISPLAY_reg: DISPLAY {
regulator-name = "DISPLAY";
};
GVDD_reg: GVDD {
/* 20v */
regulator-name = "GVDD";
};
GVEE_reg: GVEE {
/* -22v */
regulator-name = "GVEE";
};
HVINN_reg: HVINN {
/* -22v */
regulator-name = "HVINN";
};
HVINP_reg: HVINP {
/* 20v */
regulator-name = "HVINP";
};
VCOM_reg: VCOM {
regulator-name = "VCOM";
/* Real max value: -500000 */
regulator-max-microvolt = <4325000>;
/* Real min value: -4325000 */
regulator-min-microvolt = <500000>;
};
VNEG_reg: VNEG {
/* -15v */
regulator-name = "VNEG";
};
VPOS_reg: VPOS {
/* 15v */
regulator-name = "VPOS";
};
V3P3_reg: V3P3 {
regulator-name = "V3P3";
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
DCVDD-supply = <&vgen3_reg>;
DBVDD-supply = <&reg_aud3v>;
AVDD-supply = <&vgen3_reg>;
CPVDD-supply = <&vgen3_reg>;
MICVDD-supply = <&reg_aud3v>;
PLLVDD-supply = <&vgen3_reg>;
SPKVDD1-supply = <&reg_aud4v>;
SPKVDD2-supply = <&reg_aud4v>;
amic-mono;
};
};
&lcdif {
@ -252,9 +396,30 @@
pinctrl-0 = <&pinctrl_lcd>;
status = "okay";
port {
display_out: endpoint {
remote-endpoint = <&panel_in>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display0>;
display0: display@0 {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hback-porch = <89>;
hfront-porch = <164>;
vback-porch = <23>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
@ -265,6 +430,10 @@
status = "okay";
};
&pxp {
status = "okay";
};
&reg_3p0 {
vin-supply = <&sw2_reg>;
};
@ -277,12 +446,26 @@
status = "okay";
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,uart-has-rtscts;
/* for DTE mode, add below change */
/* fsl,dte-mode; */
/* pinctrl-0 = <&pinctrl_uart5dte>; */
status = "disabled";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
@ -296,6 +479,17 @@
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <8>;
non-removable;
vqmmc-supply = <&reg_sd2_vmmc>;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
pinctrl-names = "default";
@ -333,6 +527,65 @@
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
>;
};
pinctrl_audmux3: audmux3grp {
fsl,pins = <
MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
>;
};
pinctrl_epdc0: epdcgrp0 {
fsl,pins = <
MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1
MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1
MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1
MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1
MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1
MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1
MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1
MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1
MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1
MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1
MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1
MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1
MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1
MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1
MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1
MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1
MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1
MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1
MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1
MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1
MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1
MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1
MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1
MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1
MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1
>;
};
pinctrl_max17135: max17135grp-1 {
fsl,pins = <
MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */
MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */
MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */
MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */
MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */
>;
};
pinctrl_reg_sd3_vmmc: sd3vmmcgrp {
fsl,pins = <
MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059
@ -370,6 +623,25 @@
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x1b0b1 /* bt reg on */
MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1
MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1
MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1
MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart5dte: uart5dtegrp {
fsl,pins = <
MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1
MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1
MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1
MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059
@ -403,6 +675,54 @@
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059
MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059
MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059
MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059
MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059
MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059
MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059
MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059
MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059
MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
fsl,pins = <
MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9
MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9
MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9
MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9
MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9
MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9
MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9
MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9
MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9
MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9
MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
fsl,pins = <
MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9
MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9
MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9
MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9
MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9
MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9
MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9
MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9
MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9
MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9
MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
@ -452,6 +772,13 @@
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1
MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79

92
arch/arm/boot/dts/imx6sll.dtsi
View File

@ -65,13 +65,18 @@
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
fsl,low-power-run;
clocks = <&clks IMX6SLL_CLK_ARM>,
<&clks IMX6SLL_CLK_PLL2_PFD2>,
<&clks IMX6SLL_CLK_STEP>,
<&clks IMX6SLL_CLK_PLL1_SW>,
<&clks IMX6SLL_CLK_PLL1_SYS>;
<&clks IMX6SLL_CLK_PLL1_SYS>,
<&clks IMX6SLL_CLK_PLL1>,
<&clks IMX6SLL_PLL1_BYPASS>,
<&clks IMX6SLL_PLL1_BYPASS_SRC>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
"pll1_sw", "pll1_sys", "pll1", "pll1_bypass",
"pll1_bypass_src";
};
};
@ -120,9 +125,45 @@
interrupt-parent = <&gpc>;
ranges;
ocram: sram@900000 {
busfreq {
compatible = "fsl,imx_busfreq";
clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>,
<&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>,
<&clks IMX6SLL_CLK_PLL3_USB_OTG>, <&clks IMX6SLL_CLK_PERIPH>,
<&clks IMX6SLL_CLK_PERIPH_PRE>, <&clks IMX6SLL_CLK_PERIPH_CLK2>,
<&clks IMX6SLL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SLL_CLK_OSC>,
<&clks IMX6SLL_CLK_AHB>, <&clks IMX6SLL_CLK_AXI_PODF>,
<&clks IMX6SLL_CLK_PERIPH2>, <&clks IMX6SLL_CLK_PERIPH2_PRE>,
<&clks IMX6SLL_CLK_PERIPH2_CLK2>, <&clks IMX6SLL_CLK_PERIPH2_CLK2_SEL>,
<&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_MMDC_P0_FAST>, <&clks IMX6SLL_PLL1_BYPASS_SRC>,
<&clks IMX6SLL_PLL1_BYPASS>, <&clks IMX6SLL_CLK_PLL1_SYS>, <&clks IMX6SLL_CLK_PLL1_SW>,
<&clks IMX6SLL_CLK_PLL1>;
clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
"periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
"ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
"step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1";
fsl,max_ddr_freq = <400000000>;
};
ocrams: sram@900000 {
compatible = "fsl,lpm-sram";
reg = <0x900000 0x4000>;
};
ocrams_ddr: sram@904000 {
compatible = "fsl,ddr-lpm-sram";
reg = <0x904000 0x1000>;
};
ocram: sram@905000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
reg = <0x905000 0x1B000>;
};
ocram_optee: sram@918000 {
compatible = "fsl,optee-lpm-sram";
reg = <0x918000 0x8000>;
overw_reg = <&ocram 0x905000 0x13000>;
};
intc: interrupt-controller@a01000 {
@ -183,7 +224,7 @@
};
ecspi1: spi@2008000 {
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
compatible ="fsl,imx51-ecspi";
reg = <0x02008000 0x4000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
@ -195,7 +236,7 @@
};
ecspi2: spi@200c000 {
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
compatible = "fsl,imx51-ecspi";
reg = <0x0200c000 0x4000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
@ -207,7 +248,7 @@
};
ecspi3: spi@2010000 {
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
compatible = "fsl,imx51-ecspi";
reg = <0x02010000 0x4000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
@ -219,7 +260,7 @@
};
ecspi4: spi@2014000 {
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
compatible = "fsl,imx51-ecspi";
reg = <0x02014000 0x4000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
@ -621,7 +662,7 @@
};
sdma: dma-controller@20ec000 {
compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_IPG>,
@ -632,6 +673,26 @@
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
};
pxp: pxp@20f0000 {
compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
reg = <0x20f0000 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_DUMMY>,
<&clks IMX6SLL_CLK_PXP>;
clock-names = "pxp_ipg", "pxp_axi";
status = "disabled";
};
epdc: epdc@20f4000 {
compatible = "fsl,imx6sll-epdc", "fsl,imx7d-epdc";
reg = <0x20f4000 0x4000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_EPDC_AXI>, <&clks IMX6SLL_CLK_EPDC_PIX>;
clock-names = "epdc_axi", "epdc_pix";
status = "disabled";
};
lcdif: lcd-controller@20f8000 {
compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
reg = <0x020f8000 0x4000>;
@ -698,7 +759,7 @@
};
usdhc1: mmc@2190000 {
compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_USDHC1>,
@ -712,7 +773,7 @@
};
usdhc2: mmc@2194000 {
compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_USDHC2>,
@ -726,7 +787,7 @@
};
usdhc3: mmc@2198000 {
compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_USDHC3>,
@ -775,6 +836,13 @@
clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
};
rngb: rng@21b4000 {
compatible = "fsl,imx25-rngb";
reg = <0x021b4000 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_DUMMY>;
};
ocotp: ocotp-ctrl@21bc000 {
#address-cells = <1>;
#size-cells = <1>;

26
arch/arm/boot/dts/imx6sx-pinfunc.h
View File

@ -66,6 +66,7 @@
#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0
#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0
#define MX6SX_PAD_GPIO1_IO06__UART1_CTS_B 0x002C 0x0374 0x0000 0x4 0x0
#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0
@ -75,6 +76,7 @@
#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0
#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0
#define MX6SX_PAD_GPIO1_IO07__UART1_RTS_B 0x0030 0x0378 0x082C 0x4 0x1
#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0
@ -84,6 +86,7 @@
#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0
#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1
#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0
#define MX6SX_PAD_GPIO1_IO08__UART2_CTS_B 0x0034 0x037C 0x0000 0x4 0x0
#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0
@ -93,6 +96,7 @@
#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0
#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0
#define MX6SX_PAD_GPIO1_IO09__UART2_RTS_B 0x0038 0x0380 0x0834 0x4 0x1
#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0
@ -200,6 +204,7 @@
#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2
#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0
#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0
#define MX6SX_PAD_CSI_DATA06__UART6_CTS_B 0x0064 0x03AC 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0
@ -210,6 +215,7 @@
#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2
#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0
#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_DATA07__UART6_RTS_B 0x0068 0x03B0 0x0854 0x4 0x1
#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0
@ -219,6 +225,7 @@
#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1
#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1
#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2
#define MX6SX_PAD_CSI_HSYNC__UART4_CTS_B 0x006C 0x03B4 0x0000 0x3 0x0
#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0
@ -251,6 +258,7 @@
#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1
#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1
#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0
#define MX6SX_PAD_CSI_VSYNC__UART4_RTS_B 0x0078 0x03C0 0x0844 0x3 0x3
#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0
@ -353,6 +361,7 @@
#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0
#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1
#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2
#define MX6SX_PAD_ENET2_RX_CLK__UART1_CTS_B 0x009C 0x03E4 0x0000 0x3 0x0
#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1
#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0
#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1
@ -363,6 +372,7 @@
#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1
#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1
#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0
#define MX6SX_PAD_ENET2_TX_CLK__UART1_RTS_B 0x00A0 0x03E8 0x082C 0x3 0x3
#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1
#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0
#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0
@ -372,6 +382,7 @@
#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0
#define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2
#define MX6SX_PAD_KEY_COL0__UART6_CTS_B 0x00A4 0x03EC 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0
#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0
#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0
@ -390,6 +401,7 @@
#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1
#define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2
#define MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x00AC 0x03F4 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0
#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0
#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0
@ -415,6 +427,7 @@
#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0
#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_ROW0__UART6_RTS_B 0x00B8 0x0400 0x0854 0x2 0x3
#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0
#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0
#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0
@ -434,6 +447,7 @@
#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1
#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x00C0 0x0408 0x084C 0x2 0x3
#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1
#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1
#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0
@ -816,6 +830,7 @@
#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0
#define MX6SX_PAD_NAND_DATA04__UART3_CTS_B 0x0160 0x04A8 0x0000 0x3 0x0
#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0
#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0
@ -826,6 +841,7 @@
#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0
#define MX6SX_PAD_NAND_DATA05__UART3_RTS_B 0x0164 0x04AC 0x083C 0x3 0x1
#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0
#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0
@ -968,6 +984,7 @@
#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0
#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0
#define MX6SX_PAD_QSPI1B_DATA0__UART3_RTS_B 0x01A0 0x04E8 0x083C 0x1 0x4
#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1
#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2
#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1
@ -976,6 +993,7 @@
#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5
#define MX6SX_PAD_QSPI1B_DATA1__UART3_CTS_B 0x01A4 0x04EC 0x0000 0x1 0x0
#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1
#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2
#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1
@ -1247,6 +1265,7 @@
#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0
#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0
#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0
#define MX6SX_PAD_SD1_DATA2__UART2_RTS_B 0x0230 0x0578 0x0834 0x4 0x2
#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0
#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0
#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0
@ -1256,6 +1275,7 @@
#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2
#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0
#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3
#define MX6SX_PAD_SD1_DATA3__UART2_CTS_B 0x0234 0x057C 0x0000 0x4 0x0
#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0
#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0
#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2
@ -1326,6 +1346,7 @@
#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0
#define MX6SX_PAD_SD3_CLK__UART4_RTS_B 0x0250 0x0598 0x0844 0x1 0x0
#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0
#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0
#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0
@ -1365,6 +1386,7 @@
#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1
#define MX6SX_PAD_SD3_DATA2__UART4_CTS_B 0x0260 0x05A8 0x0000 0x1 0x0
#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0
#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0
#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0
@ -1410,6 +1432,7 @@
#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0
#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0
#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2
#define MX6SX_PAD_SD3_DATA6__UART3_CTS_B 0x0270 0x05B8 0x0000 0x3 0x0
#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0
@ -1420,6 +1443,7 @@
#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0
#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0
#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0
#define MX6SX_PAD_SD3_DATA7__UART3_RTS_B 0x0274 0x05BC 0x083C 0x3 0x3
#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0
@ -1511,6 +1535,7 @@
#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0
#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0
#define MX6SX_PAD_SD4_DATA6__UART5_CTS_B 0x0298 0x05E0 0x0000 0x2 0x0
#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0
#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0
@ -1521,6 +1546,7 @@
#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0
#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0
#define MX6SX_PAD_SD4_DATA7__UART5_RTS_B 0x029C 0x05E4 0x084C 0x2 0x1
#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0
#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0

346
arch/arm/boot/dts/imx6sx-sabreauto.dts
View File

@ -66,12 +66,153 @@
enable-active-high;
vin-supply = <&reg_can_en>;
};
reg_vref_3v3: regulator-adc-verf {
compatible = "regulator-fixed";
regulator-name = "vref-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_audio: cs42888_supply {
compatible = "regulator-fixed";
regulator-name = "cs42888_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
si4763_vio1: vio1_tnr {
compatible = "regulator-fixed";
regulator-name = "vio1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
si4763_vio2: vio2_tnr {
compatible = "regulator-fixed";
regulator-name = "vio2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
si4763_vd: f3v3_tnr {
compatible = "regulator-fixed";
regulator-name = "vd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
si4763_va: f5v_tnr {
compatible = "regulator-fixed";
regulator-name = "va";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
sound-cs42888 {
compatible = "fsl,imx6-sabreauto-cs42888",
"fsl,imx-audio-cs42888";
model = "imx-cs42888";
esai-controller = <&esai>;
asrc-controller = <&asrc>;
audio-codec = <&codec>;
};
sound-fm {
compatible = "fsl,imx-audio-si476x",
"fsl,imx-tuner-si476x";
model = "imx-radio-si4763";
ssi-controller = <&ssi2>;
fm-controller = <&si476x_codec>;
mux-int-port = <2>;
mux-ext-port = <5>;
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-in;
};
};
&adc1 {
vref-supply = <&reg_vref_3v3>;
status = "okay";
};
&adc2 {
vref-supply = <&reg_vref_3v3>;
status = "okay";
};
&anaclk2 {
clock-frequency = <24576000>;
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_3>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>,
<&clks IMX6SX_PLL4_BYPASS>,
<&clks IMX6SX_CLK_PLL4_POST_DIV>;
assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>,
<&clks IMX6SX_PLL4_BYPASS_SRC>;
assigned-clock-rates = <0>, <0>, <24576000>;
};
&esai {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esai_2>;
assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>,
<&clks IMX6SX_CLK_ESAI_EXTAL>;
assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>, <24576000>;
status = "okay";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif_3>;
status = "okay";
};
&ssi2 {
fsl,mode = "i2s-master";
status = "okay";
};
&csi2 {
status = "okay";
port {
csi2_ep: endpoint {
remote-endpoint = <&vadc_ep>;
};
};
};
&dcic1 {
dcic_id = <0>;
dcic_mux = "dcic-lcdif1";
status = "okay";
};
&dcic2 {
dcic_id = <1>;
dcic_mux = "dcic-lvds";
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
@ -87,11 +228,13 @@
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,eee-disabled;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
at803x,eee-disabled;
};
};
};
@ -119,12 +262,62 @@
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
nand-on-flash-bbt;
status = "okay";
};
&qspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_1>;
status = "okay";
ddrsmp=<2>;
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <29000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
};
flash1: n25q256a@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <29000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <2>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 { /* for bluetooth */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,uart-has-rtscts;
status = "okay";
/* for DTE mode, add below change */
/* fsl,dte-mode;*/
/* pinctrl-0 = <&pinctrl_uart5dte>; */
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
@ -151,6 +344,14 @@
};
&iomuxc {
pinctrl_audmux_3: audmux-3 {
fsl,pins = <
MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0
MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0
MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0
>;
};
pinctrl_egalax_int: egalax-intgrp {
fsl,pins = <
MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0
@ -193,6 +394,27 @@
>;
};
pinctrl_esai_2: esaigrp-2 {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
>;
};
pinctrl_spdif_3: spdifgrp-3 {
fsl,pins = <
MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
@ -207,6 +429,27 @@
>;
};
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
@ -227,6 +470,23 @@
>;
};
pinctrl_qspi1_1: qspi1grp_1 {
fsl,pins = <
MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1
MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1
MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1
MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1
MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1
MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1
MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1
MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1
MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1
MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1
MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1
MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
@ -234,6 +494,31 @@
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
>;
};
pinctrl_uart5dte: uart5dtegrp {
fsl,pins = <
MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1
MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1
MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1
MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
@ -313,6 +598,31 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
codec: cs42888@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&anaclk2 0>;
clock-names = "mclk";
VA-supply = <&reg_audio>;
VD-supply = <&reg_audio>;
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
};
si4763: si4763@63 {
compatible = "si4761";
reg = <0x63>;
va-supply = <&si4763_va>;
vd-supply = <&si4763_vd>;
vio1-supply = <&si4763_vio1>;
vio2-supply = <&si4763_vio2>;
revision-a10; /* set to default A10 compatible command set */
si476x_codec: si476x-codec {
compatible = "si476x-codec";
};
};
touchscreen@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
@ -452,6 +762,42 @@
gpio-controller;
#gpio-cells = <2>;
};
mma8451@1c {
compatible = "fsl,mma8451";
reg = <0x1c>;
position = <7>;
interrupt-parent = <&gpio3>;
interrupts = <24 8>;
interrupt-route = <1>;
};
mag3110@e {
compatible = "fsl,mag3110";
reg = <0xe>;
position = <2>;
interrupt-parent = <&gpio6>;
interrupts = <6 1>;
};
isl29023@44 {
compatible = "fsl,isl29023";
reg = <0x44>;
rext = <499>;
interrupt-parent = <&gpio3>;
interrupts = <23 2>;
};
};
&vadc {
vadc_in = <0>;
csi_id = <1>;
status = "okay";
port {
vadc_ep: endpoint {
remote-endpoint = <&csi2_ep>;
};
};
};
&wdog1 {

87
arch/arm/boot/dts/imx6sx-sdb-btwifi.dts 100644
View File

@ -0,0 +1,87 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* NOTE: This DTS file is wrote for plugging in Murata 1MW M.2
* into SD2 slot by using Murata uSD-to-M.2 Adapter.
*
* By default, OOB IRQ is not enabled since i.MX6SX SDB board needs to rework.
* How to enable OOB IRQ ?
* HW rework:
* Install R328 on i.MX6SX SDB board.
* SW change:
* pinctrl_wifi: wifigrp {
* fsl,pins = <
* MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x0b001
* >;
* };
* brcmf: bcrmf@1 {
* reg = <1>;
* compatible = "brcm,bcm4329-fmac";
* interrupt-parent = <&gpio2>;
* interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
* interrupt-names = "host-wake";
* };
*/
#include "imx6sx-sdb.dts"
/ {
modem_reset: modem-reset {
compatible = "gpio-reset";
reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
#reset-cells = <0>;
};
usdhc2_pwrseq: usdhc2_pwrseq {
compatible = "mmc-pwrseq-simple";
};
};
&iomuxc {
imx6sx-sdb-murata-wifibt {
pinctrl_bt: btgrp {
fsl,pins = <
MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x13069 /* BT_REG_ON */
>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <
>;
};
};
};
&uart5 { /* for bluetooth */
pinctrl-0 = <&pinctrl_uart5 &pinctrl_bt>;
resets = <&modem_reset>;
};
&usdhc2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi>;
bus-width = <4>;
no-1-8-v; /* force 3.3V VIO */
non-removable;
mmc-pwrseq = <&usdhc2_pwrseq>;
pm-ignore-notify;
cap-power-off-card;
/delete-property/ wakeup-source;
status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};

33
arch/arm/boot/dts/imx6sx-sdb-emmc.dts 100644
View File

@ -0,0 +1,33 @@
/*
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*/
#include "imx6sx-sdb.dts"
/*
* The eMMC chip on imx6sx sdb board is DNP by default.
* Need do hw rework to burn the eMMC4.5 chip on the eMMC socket on uSDHC4
* and connect eMMC signals as well as disconnect BOOT SD CARD slot signals
*/
&usdhc4 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc4_1>;
pinctrl-1 = <&pinctrl_usdhc4_1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc4_1_200mhz>;
bus-width = <8>;
auto-cmd23-broken;
/*
* overwrite cd-gpios and wp-gpios since they are reused as eMMC DATA
* signals after rework
*/
cd-gpios = <>;
wp-gpios = <>;
non-removable;
status = "okay";
};

25
arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts 100644
View File

@ -0,0 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*/
#include "imx6sx-sdb.dts"
/ {
reg_lcd_3v3: regulator-lcd-3v3 {
status = "okay";
};
};
&csi1 {
status = "disabled";
};
&lcdif1 {
status = "okay";
};
&ov5640 {
status = "disabled";
};

39
arch/arm/boot/dts/imx6sx-sdb-ldo.dts 100644
View File

@ -0,0 +1,39 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6sx-sdb.dts"
&cpu0 {
operating-points = <
/* kHz uV */
996000 1250000
792000 1175000
396000 1075000
198000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC uV */
996000 1175000
792000 1175000
396000 1175000
198000 1175000
>;
fsl,arm-soc-shared = <0>;
};
&gpc {
fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */
};
&reg_arm {
/delete-property/ vin-supply;
};
&reg_soc {
/delete-property/ vin-supply;
};

102
arch/arm/boot/dts/imx6sx-sdb-m4.dts 100644
View File

@ -0,0 +1,102 @@
/*
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6sx-sdb.dts"
/{
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
m4_reserved: m4@0x80000000 {
no-map;
reg = <0x9ff00000 0x100000>;
};
rpmsg_reserved: rpmsg@0xbff00000 {
no-map;
reg = <0xbff00000 0x100000>;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
};
/*
* The flollowing modules are conflicting with M4, disable them when m4
* is running.
*/
&adc1 {
status = "disabled";
};
&adc2 {
status = "disabled";
};
&flexcan1 {
status = "disabled";
};
&flexcan2 {
status = "disabled";
};
&i2c3 {
status = "disabled";
};
&ocram {
reg = <0x00901000 0xf000>;
};
&qspi2 {
status = "disabled";
};
&qspi_m4 {
status = "okay";
};
&rpmsg{
vdev-nums = <1>;
reg = <0xbfff0000 0x10000>;
status = "okay";
};
&uart2 {
status = "disabled";
};
&clks {
fsl,shared-clks-number = <0x23>;
fsl,shared-clks-index = <IMX6SX_CLK_PLL2_BUS IMX6SX_CLK_PLL2_PFD0
IMX6SX_CLK_PLL2_PFD2 IMX6SX_CLK_PLL3_USB_OTG
IMX6SX_CLK_PLL3_PFD1 IMX6SX_CLK_PLL3_PFD2
IMX6SX_CLK_PLL3_PFD3 IMX6SX_CLK_PLL4_AUDIO
IMX6SX_CLK_PLL5_VIDEO
IMX6SX_CLK_OCRAM IMX6SX_CLK_CAN1_SERIAL
IMX6SX_CLK_CAN1_IPG IMX6SX_CLK_CAN2_SERIAL
IMX6SX_CLK_CAN2_IPG IMX6SX_CLK_CANFD
IMX6SX_CLK_ECSPI1 IMX6SX_CLK_ECSPI2
IMX6SX_CLK_ECSPI3 IMX6SX_CLK_ECSPI4
IMX6SX_CLK_ECSPI5 IMX6SX_CLK_QSPI1
IMX6SX_CLK_QSPI2 IMX6SX_CLK_SSI1
IMX6SX_CLK_SSI2 IMX6SX_CLK_SSI3
IMX6SX_CLK_UART_SERIAL IMX6SX_CLK_UART_IPG
IMX6SX_CLK_PERIPH_CLK2_SEL IMX6SX_CLK_DUMMY
IMX6SX_CLK_I2C1 IMX6SX_CLK_I2C2
IMX6SX_CLK_I2C3 IMX6SX_CLK_I2C4
IMX6SX_CLK_EPIT1 IMX6SX_CLK_EPIT2>;
fsl,shared-mem-addr = <0x91F000>;
fsl,shared-mem-size = <0x1000>;
};

48
arch/arm/boot/dts/imx6sx-sdb-mqs.dts 100644
View File

@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2014 Freescale Semiconductor, Inc.
#include "imx6sx-sdb.dts"
/ {
sound {
status = "disabled";
};
sound-mqs {
compatible = "fsl,imx6sx-sdb-mqs",
"fsl,imx-audio-mqs";
model = "mqs-audio";
cpu-dai = <&sai1>;
asrc-controller = <&asrc>;
audio-codec = <&mqs>;
};
};
&usdhc2 {
/* pin conflict with mqs*/
status = "disabled";
};
&mqs {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mqs>;
clocks = <&clks IMX6SX_CLK_SAI1>;
clock-names = "mclk";
status = "okay";
};
&sai1 {
pinctrl-0 = <>;
status = "okay";
};
&ssi2 {
status = "disabled";
};
&sdma {
gpr = <&gpr>;
/* SDMA event remap for SAI1 */
fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
};

21
arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts 100644
View File

@ -0,0 +1,21 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6sx-sdb-reva.dts"
&gpc {
fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */
};
&reg_arm {
/delete-property/ vin-supply;
};
&reg_soc {
/delete-property/ vin-supply;
};

19
arch/arm/boot/dts/imx6sx-sdb.dts
View File

@ -103,6 +103,23 @@
};
};
&cpu0 {
operating-points = <
/* kHz uV */
996000 1250000
792000 1175000
396000 1175000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC uV */
996000 1250000
792000 1175000
396000 1175000
>;
fsl,arm-soc-shared = <1>;
};
&qspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi2>;
@ -131,10 +148,12 @@
&reg_arm {
vin-supply = <&sw1a_reg>;
regulator-allow-bypass;
};
&reg_soc {
vin-supply = <&sw1a_reg>;
regulator-allow-bypass;
};
&reg_vdd1p1 {

366
arch/arm/boot/dts/imx6sx-sdb.dtsi
View File

@ -56,6 +56,7 @@
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
@ -93,6 +94,7 @@
regulator-name = "lcd-3v3";
gpio = <&gpio3 27 0>;
enable-active-high;
status = "disabled";
};
reg_peri_3v3: regulator-peri-3v3 {
@ -151,10 +153,22 @@
regulator-max-microvolt = <3300000>;
};
reg_vref_3v3: regulator-adc-verf {
compatible = "regulator-fixed";
regulator-name = "vref-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
pxp_v4l2_out {
compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
status = "okay";
};
sound {
compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-cpu = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
@ -165,28 +179,70 @@
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <6>;
codec-master;
hp-det-gpios = <&gpio1 17 1>;
};
panel {
compatible = "sii,43wvf1g";
backlight = <&backlight_display>;
dvdd-supply = <&reg_lcd_3v3>;
avdd-supply = <&reg_lcd_5v>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
sound-spdif {
compatible = "fsl,imx-audio-spdif",
"fsl,imx6sx-sdb-spdif";
model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-out;
};
};
&adc1 {
vref-supply = <&reg_vref_3v3>;
status = "okay";
};
&adc2 {
vref-supply = <&reg_vref_3v3>;
status = "okay";
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&csi1 {
status = "okay";
port {
csi1_ep: endpoint {
remote-endpoint = <&ov5640_ep>;
};
};
};
&csi2 {
status = "okay";
port {
csi2_ep: endpoint {
remote-endpoint = <&vadc_ep>;
};
};
};
&gpc {
fsl,ldo-bypass = <1>;
};
&dcic1 {
dcic_id = <0>;
dcic_mux = "dcic-lcdif1";
status = "okay";
};
&dcic2 {
dcic_id = <1>;
dcic_mux = "dcic-lvds";
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
@ -202,10 +258,12 @@
ethphy1: ethernet-phy@1 {
reg = <1>;
at803x,eee-disabled;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
at803x,eee-disabled;
};
};
};
@ -232,11 +290,88 @@
status = "okay";
};
&gpc {
fsl,ldo-bypass = <1>;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
ov5640: ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi_0>;
clocks = <&clks IMX6SX_CLK_CSI>;
clock-names = "csi_mclk";
AVDD-supply = <&vgen3_reg>; /* 2.8v */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
pwn-gpios = <&gpio3 28 1>;
rst-gpios = <&gpio3 27 0>;
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
port {
ov5640_ep: endpoint {
remote-endpoint = <&csi1_ep>;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
egalax_ts@4 {
compatible = "eeti,egalax_ts";
reg = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_egalax_int>;
interrupt-parent = <&gpio4>;
interrupts = <19 2>;
wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
isl29023@44 {
compatible = "fsl,isl29023";
reg = <0x44>;
rext = <499>;
interrupt-parent = <&gpio6>;
interrupts = <5 1>;
shared-interrupt;
};
mag3110@e {
compatible = "fsl,mag3110";
reg = <0xe>;
position = <2>;
interrupt-parent = <&gpio6>;
interrupts = <5 1>;
shared-interrupt;
};
mma8451@1c {
compatible = "fsl,mma8451";
reg = <0x1c>;
position = <1>;
interrupt-parent = <&gpio6>;
interrupts = <2 8>;
interrupt-route = <2>;
};
};
&i2c4 {
@ -271,11 +406,65 @@
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
status = "okay";
lcd-supply = <&reg_lcd_3v3>;
display = <&display0>;
status = "disabled";
port {
display_out: endpoint {
remote-endpoint = <&panel_in>;
display0: display@0 {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hback-porch = <89>;
hfront-porch = <164>;
vback-porch = <23>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&lcdif2 {
display = <&display1>;
disp-dev = "ldb";
status = "okay";
display1: display@1 {
bits-per-pixel = <16>;
bus-width = <18>;
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
crtc = "lcdif2";
status = "okay";
display-timings {
native-mode = <&timing1>;
timing1: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
@ -286,6 +475,10 @@
status = "okay";
};
&pxp {
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
@ -296,6 +489,12 @@
status = "disabled";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif>;
status = "okay";
};
&ssi2 {
status = "okay";
};
@ -311,6 +510,9 @@
pinctrl-0 = <&pinctrl_uart5>;
uart-has-rtscts;
status = "okay";
/* for DTE mode, add below change */
/* fsl,dte-mode;*/
/* pinctrl-0 = <&pinctrl_uart5dte_1>; */
};
&usbotg1 {
@ -374,6 +576,24 @@
&iomuxc {
imx6x-sdb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059
MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000
MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
>;
};
pinctrl_can_gpios: can-gpios {
fsl,pins = <
MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059
MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
@ -384,11 +604,38 @@
>;
};
pinctrl_csi_0: csigrp-0 {
fsl,pins = <
MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0
MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0
MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0
MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0
MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0
MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0
MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0
MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0
MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0
MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0
MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0
MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0
MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0
MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0
MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000
MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000
>;
};
pinctrl_egalax_int: egalax_intgrp {
fsl,pins = <
MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
@ -457,6 +704,13 @@
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
@ -552,6 +806,13 @@
>;
};
pinctrl_mqs: mqsgrp {
fsl,pins = <
MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0
MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0
@ -562,6 +823,12 @@
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
@ -578,6 +845,15 @@
>;
};
pinctrl_uart5dte_1: uart5dtegrp-1 {
fsl,pins = <
MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1
MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1
MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1
MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1
>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
@ -667,6 +943,51 @@
>;
};
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
>;
};
pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
>;
};
pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
@ -674,3 +995,14 @@
};
};
};
&vadc {
vadc_in = <0>;
csi_id = <1>;
status = "okay";
port {
vadc_ep: endpoint {
remote-endpoint = <&csi2_ep>;
};
};
};

258
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -82,14 +82,32 @@
<&clks IMX6SX_CLK_PLL2_PFD2>,
<&clks IMX6SX_CLK_STEP>,
<&clks IMX6SX_CLK_PLL1_SW>,
<&clks IMX6SX_CLK_PLL1_SYS>;
<&clks IMX6SX_CLK_PLL1_SYS>,
<&clks IMX6SX_CLK_PLL1>,
<&clks IMX6SX_PLL1_BYPASS>,
<&clks IMX6SX_PLL1_BYPASS_SRC>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
"pll1_sw", "pll1_sys", "pll1",
"pll1_bypass", "pll1_bypass_src";
arm-supply = <&reg_arm>;
soc-supply = <&reg_soc>;
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x14000000>;
linux,cma-default;
};
};
ckil: clock-ckil {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -160,18 +178,61 @@
interrupt-parent = <&gpc>;
ranges;
ocram_s: sram@8f8000 {
compatible = "mmio-sram";
reg = <0x008f8000 0x4000>;
busfreq {
compatible = "fsl,imx_busfreq";
clocks = <&clks IMX6SX_CLK_PLL2_BUS>, <&clks IMX6SX_CLK_PLL2_PFD2>,
<&clks IMX6SX_CLK_PLL2_198M>, <&clks IMX6SX_CLK_ARM>,
<&clks IMX6SX_CLK_PLL3_USB_OTG>, <&clks IMX6SX_CLK_PERIPH>,
<&clks IMX6SX_CLK_PERIPH_PRE>, <&clks IMX6SX_CLK_PERIPH_CLK2>,
<&clks IMX6SX_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SX_CLK_OSC>,
<&clks IMX6SX_CLK_PLL1_SYS>, <&clks IMX6SX_CLK_PERIPH2>,
<&clks IMX6SX_CLK_AHB>, <&clks IMX6SX_CLK_OCRAM_PODF>,
<&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PERIPH2_PRE>,
<&clks IMX6SX_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SX_CLK_PERIPH2_CLK2>,
<&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_MMDC_PODF>,
<&clks IMX6SX_CLK_M4>;
clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm",
"pll3_usb_otg", "periph", "periph_pre", "periph_clk2",
"periph_clk2_sel", "osc", "pll1_sys", "periph2",
"ahb", "ocram", "pll1_sw", "periph2_pre",
"periph2_clk2_sel", "periph2_clk2", "step", "mmdc",
"m4";
fsl,max_ddr_freq = <400000000>;
};
ocrams: sram@8f8000 {
compatible = "fsl,lpm-sram";
reg = <0x8f8000 0x4000>;
clocks = <&clks IMX6SX_CLK_OCRAM_S>;
};
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
ocrams_ddr: sram@900000 {
compatible = "fsl,ddr-lpm-sram";
reg = <0x900000 0x1000>;
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
ocram: sram@901000 {
compatible = "mmio-sram";
reg = <0x901000 0x1F000>;
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
ocram_mf: sram-mf@900000 {
compatible = "fsl,mega-fast-sram";
reg = <0x900000 0x20000>;
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
ocram_optee {
compatible = "fsl,optee-lpm-sram";
reg = <0x8f8000 0x4000>;
overw_reg = <&ocrams_ddr 0x904000 0x1000>,
<&ocram 0x905000 0x1b000>,
<&ocrams 0x900000 0x4000>;
overw_clock = <&ocrams &clks IMX6SX_CLK_OCRAM>;
};
intc: interrupt-controller@a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
@ -200,6 +261,23 @@
<&clks IMX6SX_CLK_GPU>;
clock-names = "bus", "core", "shader";
power-domains = <&pd_pu>;
status = "disabled";
};
gpu3d: gpu3d@1800000 {
compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu";
reg = <0x1800000 0x4000>, <0x80000000 0x0>,
<0x0 0x8000000>;
reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_3d";
clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>,
<&clks 0>;
clock-names = "gpu3d_axi_clk", "gpu3d_clk",
"gpu3d_shader_clk";
resets = <&src 0>;
reset-names = "gpu3d";
power-domains = <&pd_pu>;
};
dma_apbh: dma-apbh@1804000 {
@ -215,6 +293,11 @@
clocks = <&clks IMX6SX_CLK_APBH_DMA>;
};
caam_sm: caam-sm@100000 {
compatible = "fsl,imx6q-caam-sm";
reg = <0x100000 0x8000>;
};
gpmi: gpmi-nand@1806000{
compatible = "fsl,imx6sx-gpmi-nand";
#address-cells = <1>;
@ -333,6 +416,7 @@
};
esai: esai@2024000 {
compatible = "fsl,imx35-esai";
reg = <0x02024000 0x4000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
@ -342,6 +426,9 @@
<&clks IMX6SX_CLK_SPBA>;
clock-names = "core", "mem", "extal",
"fsys", "spba";
dmas = <&sdma 23 21 0>,
<&sdma 24 21 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -388,18 +475,27 @@
};
asrc: asrc@2034000 {
compatible = "fsl,imx53-asrc";
reg = <0x02034000 0x4000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
<&clks IMX6SX_CLK_ASRC_IPG>,
<&clks IMX6SX_CLK_SPDIF>,
<&clks IMX6SX_CLK_SPBA>;
clock-names = "mem", "ipg", "asrck", "spba";
dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
<&sdma 19 20 1>, <&sdma 20 20 1>,
<&sdma 21 20 1>, <&sdma 22 20 1>;
interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
<&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
<&clks IMX6SX_CLK_SPBA>;
clock-names = "mem", "ipg", "asrck_0",
"asrck_1", "asrck_2", "asrck_3", "asrck_4",
"asrck_5", "asrck_6", "asrck_7", "asrck_8",
"asrck_9", "asrck_a", "asrck_b", "asrck_c",
"asrck_d", "asrck_e", "asrck_f", "spba";
dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
"txa", "txb", "txc";
fsl,asrc-rate = <48000>;
fsl,asrc-width = <16>;
status = "okay";
};
};
@ -559,6 +655,12 @@
gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
};
mqs: mqs {
compatible = "fsl,imx6sx-mqs";
gpr = <&gpr>;
status = "disabled";
};
kpp: kpp@20b8000 {
compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
@ -712,6 +814,20 @@
fsl,anatop = <&anatop>;
};
irq_sec_vio: caam_secvio {
compatible = "fsl,imx6q-caam-secvio";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
jtag-tamper = "disabled";
watchdog-tamper = "enabled";
internal-boot-tamper = "enabled";
external-pin-tamper = "disabled";
};
caam_snvs: caam-snvs@20cc000 {
compatible = "fsl,imx6q-caam-snvs";
reg = <0x20cc000 0x4000>;
};
snvs: snvs@20cc000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x020cc000 0x4000>;
@ -767,6 +883,7 @@
#interrupt-cells = <3>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400240>;
clocks = <&clks IMX6SX_CLK_IPG>;
clock-names = "ipg";
@ -817,6 +934,30 @@
reg = <0x020e4000 0x4000>;
};
ldb: ldb@20e0014 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
gpr = <&gpr>;
status = "disabled";
clocks = <&clks IMX6SX_CLK_LDB_DI0>,
<&clks IMX6SX_CLK_LCDIF1_SEL>,
<&clks IMX6SX_CLK_LCDIF2_SEL>,
<&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
<&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
<&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
clock-names = "ldb_di0",
"di0_sel",
"di1_sel",
"ldb_di0_div_3_5",
"ldb_di0_div_7",
"ldb_di0_div_sel";
lvds-channel@0 {
reg = <0>;
status = "disabled";
};
};
sdma: sdma@20ec000 {
compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
reg = <0x020ec000 0x4000>;
@ -928,6 +1069,8 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
stop-mode = <&gpr 0x10 3>;
fsl,wakeup_irq = <0>;
status = "disabled";
};
@ -1037,6 +1180,10 @@
<&clks IMX6SX_CLK_ENET_PTP>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
stop-mode = <&gpr 0x10 4>;
fsl,wakeup_irq = <0>;
status = "disabled";
};
@ -1125,6 +1272,12 @@
status = "disabled";
};
qspi_m4: qspi-m4 {
compatible = "fsl,imx6sx-qspi-m4-restore";
reg = <0x021e4000 0x4000>;
status = "disabled";
};
uart2: serial@21e8000 {
compatible = "fsl,imx6sx-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
@ -1203,21 +1356,45 @@
ranges;
csi1: csi@2214000 {
compatible = "fsl,imx6s-csi";
reg = <0x02214000 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
<&clks IMX6SX_CLK_CSI>,
<&clks IMX6SX_CLK_DCIC1>;
clock-names = "disp-axi", "csi_mclk", "dcic";
clock-names = "disp-axi", "csi_mclk", "disp_dcic";
status = "disabled";
};
dcic1: dcic@220c000 {
compatible = "fsl,imx6sx-dcic";
reg = <0x220c000 0x4000>;
interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_DCIC1>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
clock-names = "dcic", "disp-axi";
gpr = <&gpr>;
status = "disabled";
};
dcic2: dcic@2210000 {
compatible = "fsl,imx6sx-dcic";
reg = <0x2210000 0x4000>;
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_DCIC2>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
clock-names = "dcic", "disp-axi";
gpr = <&gpr>;
status = "disabled";
};
pxp: pxp@2218000 {
compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
reg = <0x02218000 0x4000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_PXP_AXI>;
clock-names = "axi";
clocks = <&clks IMX6SX_CLK_PXP_AXI>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
clock-names = "pxp-axi", "disp-axi";
power-domains = <&pd_disp>;
status = "disabled";
};
@ -1273,6 +1450,7 @@
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_IPG>;
clock-names = "adc";
num-channels = <4>;
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
status = "disabled";
@ -1284,6 +1462,7 @@
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_IPG>;
clock-names = "adc";
num-channels = <4>;
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
status = "disabled";
@ -1309,6 +1488,27 @@
status = "disabled";
};
sema4: sema4@02290000 { /* sema4 */
compatible = "fsl,imx6sx-sema4";
reg = <0x02290000 0x4000>;
interrupts = <0 116 0x04>;
status = "okay";
};
mu: mu@02294000 { /* mu */
compatible = "fsl,imx6sx-mu";
reg = <0x02294000 0x4000>;
interrupts = <0 90 0x04>;
#mbox-cells = <2>;
};
mu_lp: mu_lp@02294000 { /* mu */
compatible = "fsl,imx6sx-mu-lp";
reg = <0x02294000 0x4000>;
interrupts = <0 90 0x04>;
status = "okay";
};
uart6: serial@22a0000 {
compatible = "fsl,imx6sx-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
@ -1392,4 +1592,18 @@
status = "disabled";
};
};
rpmsg: rpmsg{
compatible = "fsl,imx6sx-rpmsg";
/* up to now, the following channels are used in imx rpmsg
* - tx1/rx1: messages channel.
* - general interrupt1: remote proc finish re-init rpmsg stack
* when A core is partition reset.
*/
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu 0 1
&mu 1 1
&mu 3 1>;
status = "disabled";
};
};

10
arch/arm/boot/dts/imx6ul-14x14-evk-btwifi-oob.dts 100644
View File

@ -0,0 +1,10 @@
/*
* Copyright (C) 2017 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6ul-14x14-evk-btwifi.dts"
#include "imx6ul-evk-btwifi-oob.dtsi"

10
arch/arm/boot/dts/imx6ul-14x14-evk-btwifi.dts 100644
View File

@ -0,0 +1,10 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6ul-14x14-evk.dts"
#include "imx6ul-evk-btwifi.dtsi"

18
arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts 100644
View File

@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2015 Freescale Semiconductor, Inc.
#include "imx6ul-14x14-evk.dts"
&csi {
status = "okay";
};
&ov5640 {
status = "okay";
};
&sim2 {
status = "disabled";
};

18
arch/arm/boot/dts/imx6ul-14x14-evk-ecspi-slave.dts 100644
View File

@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2018 NXP
/*
* DTS file for ECSPI Slave Certification at i.mx6ul 14x14 evk board.
* NOTE: Because Ethernet2 use the same pins with ecspi4, so disable
* fec1/fec2 for ECSPI4 test.
*/
#include "imx6ul-14x14-evk-ecspi.dts"
/delete-node/&spidev0;
&ecspi4 {
#address-cells = <0>;
spi-slave;
};

42
arch/arm/boot/dts/imx6ul-14x14-evk-ecspi.dts 100644
View File

@ -0,0 +1,42 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2018 NXP
/*
* DTS file for ECSPI Certification at i.mx6ul 14x14 evk board.
* NOTE: Because Ethernet2 use the same pins with ecspi4, so disable
* fec1/fec2 for ECSPI4 test.
*/
#include "imx6ul-14x14-evk.dts"
&iomuxc {
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x70a1
MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x70a1
MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x70a1
MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x70a1
>;
};
};
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
status = "okay";
spidev0: spi@0 {
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <20000000>;
};
};
&fec1 {
status = "disabled";
};
&fec2 {
status = "disabled";
};

21
arch/arm/boot/dts/imx6ul-14x14-evk-emmc.dts 100644
View File

@ -0,0 +1,21 @@
/*
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*/
#include "imx6ul-14x14-evk.dts"
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_8bit>;
pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};

43
arch/arm/boot/dts/imx6ul-14x14-evk-gpmi-weim.dts 100644
View File

@ -0,0 +1,43 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2015 Freescale Semiconductor, Inc.
#include "imx6ul-14x14-evk.dts"
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "okay";
nand-on-flash-bbt;
};
&iomuxc {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
>;
};
};
&qspi {
status = "disabled";
};
&usdhc2 {
status = "disabled";
};

215
arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
View File

@ -12,6 +12,19 @@
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x6000000>;
linux,cma-default;
};
};
backlight_display: backlight-display {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
@ -20,6 +33,10 @@
status = "okay";
};
pxp_v4l2 {
compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
status = "okay";
};
reg_sd1_vmmc: regulator-sd1-vmmc {
compatible = "regulator-fixed";
@ -27,6 +44,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
@ -61,22 +79,63 @@
"LINPUT3", "Mic Jack",
"RINPUT1", "Mic Jack",
"RINPUT2", "Mic Jack";
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&sai2>;
status = "disabled";
};
dailink_master: simple-audio-card,codec {
sound-dai = <&codec>;
clocks = <&clks IMX6UL_CLK_SAI2>;
status = "disabled";
};
};
sound-wm8960 {
compatible = "fsl,imx6ul-evk-wm8960",
"fsl,imx-audio-wm8960";
model = "wm8960-audio";
cpu-dai = <&sai2>;
audio-codec = <&codec>;
asrc-controller = <&asrc>;
codec-master;
gpr = <&gpr 4 0x100000 0x100000>;
/*
* hp-det = <hp-det-pin hp-det-polarity>;
* hp-det-pin: JD1 JD2 or JD3
* hp-det-polarity = 0: hp detect high for headphone
* hp-det-polarity = 1: hp detect high for speaker
*/
hp-det = <3 0>;
hp-det-gpios = <&gpio5 4 0>;
mic-det-gpios = <&gpio5 4 0>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT2", "Mic Jack",
"LINPUT3", "Mic Jack",
"RINPUT1", "Main MIC",
"RINPUT2", "Main MIC",
"Mic Jack", "MICB",
"Main MIC", "MICB",
"CPU-Playback", "ASRC-Playback",
"Playback", "CPU-Playback",
"ASRC-Capture", "CPU-Capture",
"CPU-Capture", "Capture";
};
spi4 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4>;
status = "okay";
pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
gpio-sck = <&gpio5 11 0>;
gpio-mosi = <&gpio5 10 0>;
cs-gpios = <&gpio5 7 0>;
@ -90,20 +149,10 @@
#gpio-cells = <2>;
reg = <0>;
registers-number = <1>;
registers-default = /bits/ 8 <0x57>;
spi-max-frequency = <100000>;
};
};
panel {
compatible = "innolux,at043tn24";
backlight = <&backlight_display>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
};
&clks {
@ -111,6 +160,16 @@
assigned-clock-rates = <786432000>;
};
&csi {
status = "disabled";
port {
csi1_ep: endpoint {
remote-endpoint = <&ov5640_ep>;
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
@ -122,6 +181,28 @@
compatible = "wlf,wm8960";
reg = <0x1a>;
wlf,shared-lrclk;
clocks = <&clks IMX6UL_CLK_SAI2>;
clock-names = "mclk";
};
ov5640: ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi1>;
clocks = <&clks IMX6UL_CLK_CSI>;
clock-names = "csi_mclk";
pwn-gpios = <&gpio_spi 6 1>;
rst-gpios = <&gpio_spi 5 0>;
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
status = "disabled";
port {
ov5640_ep: endpoint {
remote-endpoint = <&csi1_ep>;
};
};
};
};
@ -183,6 +264,15 @@
mag3110@e {
compatible = "fsl,mag3110";
reg = <0x0e>;
position = <2>;
};
fxls8471@1e {
compatible = "fsl,fxls8471";
reg = <0x1e>;
position = <0>;
interrupt-parent = <&gpio5>;
interrupts = <0 8>;
};
};
@ -192,11 +282,31 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
display = <&display0>;
status = "okay";
port {
display_out: endpoint {
remote-endpoint = <&panel_in>;
display0: display@0 {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <9200000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <8>;
hback-porch = <4>;
hsync-len = <41>;
vback-porch = <2>;
vfront-porch = <4>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
@ -207,6 +317,10 @@
status = "okay";
};
&pxp {
status = "okay";
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
@ -215,7 +329,7 @@
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
@ -242,6 +356,22 @@
status = "okay";
};
&sim2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sim2>;
assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>;
assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>;
assigned-clock-rates = <240000000>;
/* GPIO_ACTIVE_HIGH/LOW:sim card voltage control
* NCN8025:Vcc = ACTIVE_HIGH?5V:3V
* TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V
*/
pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
port = <1>;
sven_low_active;
status = "okay";
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
@ -266,6 +396,8 @@
&usbotg1 {
dr_mode = "otg";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
status = "okay";
};
@ -298,7 +430,7 @@
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
wakeup-source;
status = "okay";
@ -499,6 +631,12 @@
>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
@ -547,6 +685,51 @@
>;
};
pinctrl_usdhc2_8bit: usdhc2grp_8bit {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>;
};
pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
>;
};
pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0

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/*
* Copyright (C) 2017 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6ul-9x9-evk-btwifi.dts"
#include "imx6ul-evk-btwifi-oob.dtsi"

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/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6ul-9x9-evk.dts"
#include "imx6ul-evk-btwifi.dtsi"

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/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6ul-9x9-evk.dts"
&cpu0 {
operating-points = <
/* kHz uV */
696000 1275000
528000 1175000
396000 1025000
198000 950000
>;
fsl,soc-operating-points = <
/* KHz uV */
696000 1275000
528000 1175000
396000 1175000
198000 1175000
>;
fsl,arm-soc-shared = <0>;
};
&gpc {
fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */
};
&reg_arm {
/delete-property/ vin-supply;
};
&reg_soc {
/delete-property/ vin-supply;
};

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/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx6ul.dtsi"
/ {
model = "Freescale i.MX6 UltraLite 9x9 EVK Board";
compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul";
backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
};
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x80000000 0x10000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x6000000>;
linux,cma-default;
};
};
pxp_v4l2 {
compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
status = "okay";
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_can_3v3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "can-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
};
reg_gpio_dvfs: regulator-gpio {
compatible = "regulator-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dvfs>;
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1400000>;
regulator-name = "gpio_dvfs";
regulator-type = "voltage";
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
states = <1300000 0x1 1400000 0x0>;
};
reg_sd1_vmmc: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
};
sound {
compatible = "fsl,imx6ul-evk-wm8960",
"fsl,imx-audio-wm8960";
model = "wm8960-audio";
cpu-dai = <&sai2>;
audio-codec = <&codec>;
asrc-controller = <&asrc>;
codec-master;
gpr = <&gpr 4 0x100000 0x100000>;
/*
* hp-det = <hp-det-pin hp-det-polarity>;
* hp-det-pin: JD1 JD2 or JD3
* hp-det-polarity = 0: hp detect high for headphone
* hp-det-polarity = 1: hp detect high for speaker
*/
hp-det = <3 0>;
hp-det-gpios = <&gpio5 4 0>;
mic-det-gpios = <&gpio5 4 0>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT2", "Mic Jack",
"LINPUT3", "Mic Jack",
"RINPUT1", "Main MIC",
"RINPUT2", "Main MIC",
"Mic Jack", "MICB",
"Main MIC", "MICB",
"CPU-Playback", "ASRC-Playback",
"Playback", "CPU-Playback",
"ASRC-Capture", "CPU-Capture",
"CPU-Capture", "Capture";
};
spi4 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4>;
pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
status = "okay";
gpio-sck = <&gpio5 11 0>;
gpio-mosi = <&gpio5 10 0>;
cs-gpios = <&gpio5 7 0>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
gpio_spi: gpio_spi@0 {
compatible = "fairchild,74hc595";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
registers-number = <1>;
registers-default = /bits/ 8 <0x57>;
spi-max-frequency = <100000>;
};
};
};
&clks {
assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <786432000>;
};
&cpu0 {
/*
* on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN,
* to align with other platform and use the same cpufreq
* driver, still use the seperated OPP define for arm
* and soc.
*/
operating-points = <
/* kHz uV */
528000 1175000
396000 1175000
198000 1175000
>;
fsl,soc-operating-points = <
/* KHz uV */
528000 1175000
396000 1175000
198000 1175000
>;
fsl,arm-soc-shared = <1>;
};
&reg_arm {
vin-supply = <&sw1c_reg>;
regulator-allow-bypass;
};
&reg_soc {
vin-supply = <&sw1c_reg>;
regulator-allow-bypass;
};
&csi {
status = "disabled";
port {
csi1_ep: endpoint {
remote-endpoint = <&ov5640_ep>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can_3v3>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can_3v3>;
status = "okay";
};
&gpc {
fsl,cpu_pupscr_sw2iso = <0xf>;
fsl,cpu_pupscr_sw = <0x0>;
fsl,cpu_pdnscr_iso2sw = <0x1>;
fsl,cpu_pdnscr_iso = <0x1>;
fsl,ldo-bypass = <1>;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze3000@8 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
/* use sw1c_reg to align with pfuze100/pfuze200 */
sw1c_reg: sw1b {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen2_reg: vldo2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen3_reg: vccsd {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
mag3110@e {
compatible = "fsl,mag3110";
reg = <0x0e>;
position = <2>;
};
fxls8471@1e {
compatible = "fsl,fxls8471";
reg = <0x1e>;
position = <0>;
interrupt-parent = <&gpio5>;
interrupts = <0 8>;
};
};
&i2c2 {
clock_frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
codec: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clks IMX6UL_CLK_SAI2>;
clock-names = "mclk";
wlf,shared-lrclk;
};
ov5640: ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi1>;
clocks = <&clks IMX6UL_CLK_CSI>;
clock-names = "csi_mclk";
pwn-gpios = <&gpio_spi 6 1>;
rst-gpios = <&gpio_spi 5 0>;
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
status = "disabled";
port {
ov5640_ep: endpoint {
remote-endpoint = <&csi1_ep>;
};
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1>;
imx6ul-evk {
pinctrl_csi1: csi1grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
>;
};
pinctrl_dvfs: dvfsgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000
>;
};
pinctrl_flexcan1: flexcan1grp{
fsl,pins = <
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
>;
};
pinctrl_flexcan2: flexcan2grp{
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
/* used for lcd reset */
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
>;
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
>;
};
pinctrl_sim2_1: sim2grp-1 {
fsl,pins = <
MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
>;
};
pinctrl_spi4: spi4grp {
fsl,pins = <
MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
>;
};
pinctrl_tsc: tscgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
>;
};
pinctrl_uart2dte: uart2dtegrp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1
MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
>;
};
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
display = <&display0>;
status = "okay";
display0: display {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <9200000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <8>;
hback-porch = <4>;
hsync-len = <41>;
vback-porch = <2>;
vfront-porch = <4>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pxp {
status = "okay";
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
ddrsmp=<0>;
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <6>;
reg = <0>;
};
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
<&clks IMX6UL_CLK_SAI2>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>, <12288000>;
status = "okay";
};
&sim2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sim2_1>;
assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>;
assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>;
assigned-clock-rates = <240000000>;
pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
port = <1>;
sven_low_active;
status = "okay";
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure_delay_time = <0xffff>;
pre_charge_time = <0xfff>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
/* for DTE mode, add below change */
/* fsl,dte-mode; */
/* pinctrl-0 = <&pinctrl_uart2dte>; */
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
enable-sdio-wakeup;
vmmc-supply = <&reg_sd1_vmmc>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
enable-sdio-wakeup;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};

30
arch/arm/boot/dts/imx6ul-evk-btwifi-oob.dtsi 100644
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@ -0,0 +1,30 @@
/*
* Copyright 2017-2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&pinctrl_wifi {
fsl,pins = <
/* MUXing for WL_HOST_WAKE */
MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0b001 /* input: 100K Pull-up */
>;
};
/*
* For WL_HOST_WAKE (OOB_IRQ) to function correctly, we must disable
* the secondary ethernet port (FEC2). Hardware re-work is to remove
* R1633 and populate R1704 with 0 Ohm resistor.
* Refer to Murata Hardware Reference Manual for more details.
*/
&fec2 {
status = "disabled";
};
&brcmf {
interrupt-parent = <&gpio2>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>; /* M.2 WL_HOST_WAKE is active low */
interrupt-names = "host-wake";
};

72
arch/arm/boot/dts/imx6ul-evk-btwifi.dtsi 100644
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@ -0,0 +1,72 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* NOTE: This DTS file is written for plugging in Murata Wi-Fi/BT EVK into Slot
* SD1 and using Murata i.MX InterConnect Ver 2.0 Adapter. Bluetooth UART &
* control signals are connected via ribbon cable (J1701 connector).
*/
/ {
modem_reset: modem-reset {
compatible = "gpio-reset";
reset-gpios = <&gpio_spi 4 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
#reset-cells = <0>;
};
usdhc1_pwrseq: usdhc1_pwrseq {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi>;
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
};
};
&iomuxc {
pinctrl_wifi: wifigrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x03029
>;
};
};
&reg_sd1_vmmc {
regulator-always-on;
};
&uart2 {
resets = <&modem_reset>;
};
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
no-1-8-v;
non-removable;
pm-ignore-notify;
mmc-pwrseq = <&usdhc1_pwrseq>;
cap-power-off-card;
/delete-property/ wakeup-source;
/delete-property/ enable-sdio-wakeup;
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
&gpio_spi {
/* Murata: modify default setting so that BT_nPWD/BT_REG_ON
* is low (0V) during kernel boot.
*/
registers-default = /bits/ 8 <0x47>;
};

131
arch/arm/boot/dts/imx6ul.dtsi
View File

@ -82,10 +82,15 @@
<&clks IMX6UL_CA7_SECONDARY_SEL>,
<&clks IMX6UL_CLK_STEP>,
<&clks IMX6UL_CLK_PLL1_SW>,
<&clks IMX6UL_CLK_PLL1_SYS>;
<&clks IMX6UL_CLK_PLL1_SYS>,
<&clks IMX6UL_PLL1_BYPASS>,
<&clks IMX6UL_CLK_PLL1>,
<&clks IMX6UL_PLL1_BYPASS_SRC>,
<&clks IMX6UL_CLK_OSC>;
clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
"secondary_sel", "step", "pll1_sw",
"pll1_sys";
"pll1_sys", "pll1_bypass", "pll1",
"pll1_bypass_src", "osc";
arm-supply = <&reg_arm>;
soc-supply = <&reg_soc>;
nvmem-cells = <&cpu_speed_grade>;
@ -154,9 +159,43 @@
interrupt-parent = <&gpc>;
ranges;
ocram: sram@900000 {
busfreq {
compatible = "fsl,imx_busfreq";
clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>,
<&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>,
<&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>,
<&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>,
<&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>,
<&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>,
<&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>,
<&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>,
<&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>;
clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
"periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
"ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
"step", "mmdc";
fsl,max_ddr_freq = <400000000>;
};
ocrams: sram@900000 {
compatible = "fsl,lpm-sram";
reg = <0x900000 0x4000>;
};
ocrams_ddr: sram@904000 {
compatible = "fsl,ddr-lpm-sram";
reg = <0x904000 0x1000>;
};
ocram: sram@905000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
reg = <0x00905000 0x1B000>;
};
ocram_optee: sram@918000 {
compatible = "fsl,optee-lpm-sram";
reg = <0x918000 0x8000>;
overw_reg = <&ocram 0x905000 0x13000>;
};
intc: interrupt-controller@a01000 {
@ -184,6 +223,11 @@
clocks = <&clks IMX6UL_CLK_APBHDMA>;
};
caam_sm: caam-sm@100000 {
compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm";
reg = <0x100000 0x8000>;
};
gpmi: gpmi-nand@1806000 {
compatible = "fsl,imx6q-gpmi-nand";
#address-cells = <1>;
@ -351,6 +395,31 @@
dma-names = "rx", "tx";
status = "disabled";
};
asrc: asrc@2034000 {
compatible = "fsl,imx53-asrc";
reg = <0x2034000 0x4000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
<&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
<&clks IMX6UL_CLK_SPBA>;
clock-names = "mem", "ipg", "asrck_0",
"asrck_1", "asrck_2", "asrck_3", "asrck_4",
"asrck_5", "asrck_6", "asrck_7", "asrck_8",
"asrck_9", "asrck_a", "asrck_b", "asrck_c",
"asrck_d", "asrck_e", "asrck_f", "spba";
dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
fsl,asrc-rate = <48000>;
fsl,asrc-width = <16>;
status = "okay";
};
};
tsc: tsc@2040000 {
@ -520,6 +589,9 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
stop-mode = <&gpr 0x10 4>;
fsl,magic-packet;
fsl,wakeup_irq = <0>;
status = "disabled";
};
@ -631,6 +703,20 @@
fsl,anatop = <&anatop>;
};
irq_sec_vio: caam_secvio {
compatible = "fsl,imx6q-caam-secvio";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
jtag-tamper = "disabled";
watchdog-tamper = "enabled";
internal-boot-tamper = "enabled";
external-pin-tamper = "disabled";
};
caam_snvs: caam-snvs@20cc000 {
compatible = "fsl,imx6q-caam-snvs";
reg = <0x20cc000 0x4000>;
};
snvs: snvs@20cc000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x020cc000 0x4000>;
@ -855,6 +941,16 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
stop-mode = <&gpr 0x10 3>;
fsl,magic-packet;
fsl,wakeup_irq = <0>;
status = "disabled";
};
sim1: sim@0218c000 {
compatible = "fsl,imx6ul-sim";
reg = <0x0218c000 0x4000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -934,6 +1030,15 @@
clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
};
sim2: sim@021b4000 {
compatible = "fsl,imx6ul-sim";
reg = <0x021b4000 0x4000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_SIM2>;
clock-names = "sim";
status = "disabled";
};
weim: weim@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
@ -966,11 +1071,13 @@
};
csi: csi@21c4000 {
compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
compatible = "fsl,imx6ul-csi", "fsl,imx7-csi", "fsl,imx6s-csi";
reg = <0x021c4000 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_CSI>;
clock-names = "mclk";
clocks = <&clks IMX6UL_CLK_DUMMY>,
<&clks IMX6UL_CLK_CSI>,
<&clks IMX6UL_CLK_DUMMY>;
clock-names = "disp-axi", "csi_mclk", "disp_dcic";
status = "disabled";
};
@ -986,11 +1093,13 @@
};
pxp: pxp@21cc000 {
compatible = "fsl,imx6ul-pxp";
reg = <0x021cc000 0x4000>;
compatible = "fsl,imx6ul-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
reg = <0x21cc000 0x4000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_PXP>;
clock-names = "axi";
clocks = <&clks IMX6UL_CLK_PXP>,
<&clks IMX6UL_CLK_DUMMY>;
clock-names = "pxp-axi", "disp-axi";
status = "disabled";
};
qspi: spi@21e0000 {

10
arch/arm/boot/dts/imx6ull-14x14-evk-btwifi-oob.dts 100644
View File

@ -0,0 +1,10 @@
/*
* Copyright (C) 2017 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6ull-14x14-evk-btwifi.dts"
#include "imx6ul-evk-btwifi-oob.dtsi"

10
arch/arm/boot/dts/imx6ull-14x14-evk-btwifi.dts 100644
View File

@ -0,0 +1,10 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6ull-14x14-evk.dts"
#include "imx6ul-evk-btwifi.dtsi"

21
arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts 100644
View File

@ -0,0 +1,21 @@
/*
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*/
#include "imx6ull-14x14-evk.dts"
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_8bit>;
pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};

43
arch/arm/boot/dts/imx6ull-14x14-evk-gpmi-weim.dts 100644
View File

@ -0,0 +1,43 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2016 Freescale Semiconductor, Inc.
#include "imx6ull-14x14-evk.dts"
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "okay";
nand-on-flash-bbt;
};
&iomuxc {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
>;
};
};
&qspi {
status = "disabled";
};
&usdhc2 {
status = "disabled";
};

33
arch/arm/boot/dts/imx6ull-14x14-evk.dts
View File

@ -8,11 +8,38 @@
#include "imx6ul-14x14-evk.dtsi"
/ {
model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board";
model = "Freescale i.MX6 ULL 14x14 EVK Board";
compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
};
&clks {
assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>;
assigned-clock-rates = <320000000>;
assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>,
<&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <320000000>, <786432000>;
};
&csi {
status = "okay";
};
&iomuxc {
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
>;
};
};
&ov5640 {
status = "okay";
};
/delete-node/ &sim2;

10
arch/arm/boot/dts/imx6ull-9x9-evk-btwifi-oob.dts 100644
View File

@ -0,0 +1,10 @@
/*
* Copyright (C) 2017 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6ull-9x9-evk-btwifi.dts"
#include "imx6ul-evk-btwifi-oob.dtsi"

10
arch/arm/boot/dts/imx6ull-9x9-evk-btwifi.dts 100644
View File

@ -0,0 +1,10 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6ull-9x9-evk.dts"
#include "imx6ul-evk-btwifi.dtsi"

36
arch/arm/boot/dts/imx6ull-9x9-evk-ldo.dts 100644
View File

@ -0,0 +1,36 @@
/*
* Copyright (C) 2017 NXP.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6ull-9x9-evk.dts"
&cpu0 {
operating-points = <
/* kHz uV */
528000 1175000
396000 1025000
198000 950000
>;
fsl,soc-operating-points = <
/* KHz uV */
528000 1175000
396000 1175000
198000 1175000
>;
fsl,arm-soc-shared = <0>;
};
&gpc {
fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */
};
&reg_arm {
/delete-property/ vin-supply;
};
&reg_soc {
/delete-property/ vin-supply;
};

813
arch/arm/boot/dts/imx6ull-9x9-evk.dts 100644
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/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx6ull.dtsi"
/ {
model = "Freescale i.MX6 ULL 9x9 EVK Board";
compatible = "fsl,imx6ull-9x9-evk", "fsl,imx6ull";
backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
};
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x80000000 0x10000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x6000000>;
linux,cma-default;
};
};
pxp_v4l2 {
compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
status = "okay";
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_can_3v3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "can-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
};
reg_gpio_dvfs: regulator-gpio {
compatible = "regulator-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dvfs>;
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1400000>;
regulator-name = "gpio_dvfs";
regulator-type = "voltage";
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
states = <1300000 0x1 1400000 0x0>;
};
reg_sd1_vmmc: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
};
sound {
compatible = "fsl,imx6ul-evk-wm8960",
"fsl,imx-audio-wm8960";
model = "wm8960-audio";
cpu-dai = <&sai2>;
audio-codec = <&codec>;
asrc-controller = <&asrc>;
codec-master;
gpr = <&gpr 4 0x100000 0x100000>;
/*
* hp-det = <hp-det-pin hp-det-polarity>;
* hp-det-pin: JD1 JD2 or JD3
* hp-det-polarity = 0: hp detect high for headphone
* hp-det-polarity = 1: hp detect high for speaker
*/
hp-det = <3 0>;
hp-det-gpios = <&gpio5 4 0>;
mic-det-gpios = <&gpio5 4 0>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT2", "Mic Jack",
"LINPUT3", "Mic Jack",
"RINPUT1", "Main MIC",
"RINPUT2", "Main MIC",
"Mic Jack", "MICB",
"Main MIC", "MICB",
"CPU-Playback", "ASRC-Playback",
"Playback", "CPU-Playback",
"ASRC-Capture", "CPU-Capture",
"CPU-Capture", "Capture";
};
spi4 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4>;
pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
status = "okay";
gpio-sck = <&gpio5 11 0>;
gpio-mosi = <&gpio5 10 0>;
cs-gpios = <&gpio5 7 0>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
gpio_spi: gpio_spi@0 {
compatible = "fairchild,74hc595";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
registers-number = <1>;
registers-default = /bits/ 8 <0x57>;
spi-max-frequency = <100000>;
};
};
};
&clks {
assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <786432000>;
};
&cpu0 {
/*
* on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN,
* to align with other platform and use the same cpufreq
* driver, still use the seperated OPP define for arm
* and soc.
*/
operating-points = <
/* kHz uV */
528000 1175000
396000 1175000
198000 1175000
>;
fsl,soc-operating-points = <
/* KHz uV */
528000 1175000
396000 1175000
198000 1175000
>;
fsl,arm-soc-shared = <1>;
};
&reg_arm {
vin-supply = <&sw1c_reg>;
regulator-allow-bypass;
};
&reg_soc {
vin-supply = <&sw1c_reg>;
regulator-allow-bypass;
};
&csi {
status = "okay";
port {
csi1_ep: endpoint {
remote-endpoint = <&ov5640_ep>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can_3v3>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can_3v3>;
status = "okay";
};
&gpc {
fsl,cpu_pupscr_sw2iso = <0xf>;
fsl,cpu_pupscr_sw = <0x0>;
fsl,cpu_pdnscr_iso2sw = <0x1>;
fsl,cpu_pdnscr_iso = <0x1>;
fsl,ldo-bypass = <1>;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze3000@8 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
/* use sw1c_reg to align with pfuze100/pfuze200 */
sw1c_reg: sw1b {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen2_reg: vldo2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen3_reg: vccsd {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
mag3110@e {
compatible = "fsl,mag3110";
reg = <0x0e>;
position = <2>;
};
fxls8471@1e {
compatible = "fsl,fxls8471";
reg = <0x1e>;
position = <0>;
interrupt-parent = <&gpio5>;
interrupts = <0 8>;
};
};
&i2c2 {
clock_frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
codec: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clks IMX6UL_CLK_SAI2>;
clock-names = "mclk";
wlf,shared-lrclk;
};
ov5640: ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi1>;
clocks = <&clks IMX6UL_CLK_CSI>;
clock-names = "csi_mclk";
pwn-gpios = <&gpio_spi 6 1>;
rst-gpios = <&gpio_spi 5 0>;
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
status = "okay";
port {
ov5640_ep: endpoint {
remote-endpoint = <&csi1_ep>;
};
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1>;
imx6ul-evk {
pinctrl_csi1: csi1grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
>;
};
pinctrl_flexcan1: flexcan1grp{
fsl,pins = <
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
>;
};
pinctrl_flexcan2: flexcan2grp{
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
>;
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
>;
};
pinctrl_tsc: tscgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
>;
};
pinctrl_uart2dte: uart2dtegrp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1
MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
>;
};
};
};
&iomuxc_snvs {
pinctrl-names = "default_snvs";
pinctrl-0 = <&pinctrl_hog_2>;
imx6ull-evk {
pinctrl_hog_2: hoggrp-2 {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000
>;
};
pinctrl_dvfs: dvfsgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
>;
};
pinctrl_lcdif_reset: lcdifresetgrp {
fsl,pins = <
/* used for lcd reset */
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
>;
};
pinctrl_spi4: spi4grp {
fsl,pins = <
MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
>;
};
pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
>;
};
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl
&pinctrl_lcdif_reset>;
display = <&display0>;
status = "okay";
display0: display {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <9200000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <8>;
hback-porch = <4>;
hsync-len = <41>;
vback-porch = <2>;
vfront-porch = <4>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pxp {
status = "okay";
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
ddrsmp=<0>;
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <6>;
reg = <0>;
};
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2
&pinctrl_sai2_hp_det_b>;
assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
<&clks IMX6UL_CLK_SAI2>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>, <12288000>;
status = "okay";
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure_delay_time = <0xffff>;
pre_charge_time = <0xfff>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
/* for DTE mode, add below change */
/* fsl,dte-mode; */
/* pinctrl-0 = <&pinctrl_uart2dte>; */
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
enable-sdio-wakeup;
vmmc-supply = <&reg_sd1_vmmc>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
enable-sdio-wakeup;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};

52
arch/arm/boot/dts/imx6ull.dtsi
View File

@ -36,21 +36,50 @@
};
&pxp {
compatible = "fsl,imx6ull-pxp";
compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_PXP>;
clock-names = "pxp_ipg", "pxp_axi";
status = "disabled";
};
&usdhc1 {
compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <132000000>;
};
&usdhc2 {
compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <132000000>;
};
/ {
soc {
busfreq {
compatible = "fsl,imx_busfreq";
clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>,
<&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>,
<&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>,
<&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>,
<&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>,
<&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>,
<&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>,
<&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>,
<&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>, <&clks IMX6UL_PLL1_BYPASS_SRC>,
<&clks IMX6UL_PLL1_BYPASS>, <&clks IMX6UL_CLK_PLL1_SYS>, <&clks IMX6UL_CLK_PLL1_SW>,
<&clks IMX6UL_CLK_PLL1>;
clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
"periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
"ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
"step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1";
fsl,max_ddr_freq = <400000000>;
};
aips3: aips-bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
@ -68,6 +97,13 @@
clock-names = "dcp";
};
rngb: rng@2284000 {
compatible = "fsl,imx25-rngb";
reg = <0x02284000 0x4000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_DUMMY>;
};
iomuxc_snvs: iomuxc-snvs@2290000 {
compatible = "fsl,imx6ull-iomuxc-snvs";
reg = <0x02290000 0x4000>;
@ -83,6 +119,18 @@
clock-names = "ipg", "per";
status = "disabled";
};
epdc: epdc@228c000 {
compatible = "fsl,imx7d-epdc";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x228c000 0x4000>;
clocks = <&clks IMX6ULL_CLK_EPDC_ACLK>,
<&clks IMX6ULL_CLK_EPDC_PIX>;
clock-names = "epdc_axi", "epdc_pix";
/* Need to fix epdc-ram */
/* epdc-ram = <&gpr 0x4 30>; */
status = "disabled";
};
};
};
};

16
arch/arm/boot/dts/imx6ulz-14x14-evk-btwifi.dts 100644
View File

@ -0,0 +1,16 @@
/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "imx6ulz-14x14-evk.dts"
#include "imx6ul-evk-btwifi.dtsi"

25
arch/arm/boot/dts/imx6ulz-14x14-evk-emmc.dts 100644
View File

@ -0,0 +1,25 @@
/*
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "imx6ulz-14x14-evk.dts"
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_8bit>;
pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};

43
arch/arm/boot/dts/imx6ulz-14x14-evk-gpmi-weim.dts 100644
View File

@ -0,0 +1,43 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2018 NXP
#include "imx6ulz-14x14-evk.dts"
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "okay";
nand-on-flash-bbt;
};
&iomuxc {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
>;
};
};
&qspi {
status = "disabled";
};
&usdhc2 {
status = "disabled";
};

17
arch/arm/boot/dts/imx6ulz-14x14-evk.dts
View File

@ -20,3 +20,20 @@
/delete-node/ panel;
};
&iomuxc {
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
>;
};
};

43
arch/arm/boot/dts/imx7d-12x12-lpddr3-val-sai.dts 100644
View File

@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*/
#include "imx7d-12x12-lpddr3-val.dts"
/ {
sound {
compatible = "fsl,imx7d-12x12-lpddr3-arm2-wm8958",
"fsl,imx-audio-wm8958";
model = "wm8958-audio";
cpu-dai = <&sai1>;
audio-codec = <&codec>;
codec-master;
hp-det-gpios = <&gpio1 12 1>;
};
};
&iomuxc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_headphone_det>;
pinctrl-1 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect>;
};
&sai1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai1>;
pinctrl-1 = <&pinctrl_sai1>;
status = "okay";
};
&sdma {
status = "okay";
};
&sim1 {
status = "disabled";
};
&usdhc2 {
no-1-8-v;
};

1015
arch/arm/boot/dts/imx7d-12x12-lpddr3-val.dts 100644
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7
arch/arm/boot/dts/imx7d-sdb-epdc.dts 100644
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*/
#include "imx7d-sdb.dts"
#include "imx7d-sdb-epdc.dtsi"

60
arch/arm/boot/dts/imx7d-sdb-epdc.dtsi 100644
View File

@ -0,0 +1,60 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*/
&epdc {
status = "okay";
};
&fec1 {
status = "okay";
};
&fec2 {
status = "disabled";
};
&reg_can2_3v3 {
status = "disabled";
};
&reg_fec2_3v3 {
status = "disabled";
};
&flexcan2 {
status = "disabled";
};
&max17135 {
status = "okay";
};
&sii902x {
status = "disabled";
};
&sim1 {
status = "disabled";
};
&uart5 {
status = "disabled";
};
&i2c3 {
elan@10 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_epdc_elan_touch>;
compatible = "elan,elan-touch";
reg = <0x10>;
interrupt-parent = <&gpio6>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
gpio_elan_cs = <&gpio6 13 0>;
gpio_elan_rst = <&gpio6 15 0>;
gpio_intr = <&gpio6 12 0>;
status = "okay";
};
};

9
arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dts 100644
View File

@ -0,0 +1,9 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx7d-sdb.dts"
#include "imx7d-sdb-gpmi-weim.dtsi"

23
arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dtsi 100644
View File

@ -0,0 +1,23 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&gpmi{
status = "okay";
};
/* &sai1{ */
/* status = "disabled"; */
/* }; */
&usdhc3{
status = "disabled";
};
&uart5{
status = "disabled";
};

9
arch/arm/boot/dts/imx7d-sdb-m4.dts 100644
View File

@ -0,0 +1,9 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx7d-sdb.dts"
#include "imx7d-sdb-m4.dtsi"

79
arch/arm/boot/dts/imx7d-sdb-m4.dtsi 100644
View File

@ -0,0 +1,79 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
m4_reserved: m4@0x9ff00000 {
no-map;
reg = <0x9ff00000 0x100000>;
};
rpmsg_reserved: rpmsg@0xbff00000 {
no-map;
reg = <0xbff00000 0x100000>;
};
};
m4_tcm: tcml@007f8000 {
compatible = "fsl, m4_tcml";
reg = <0x007f8000 0x8000>;
};
};
&adc1 {
status = "disabled";
};
&adc2 {
status = "disabled";
};
&flexcan1 {
status = "disabled";
};
&flexcan2 {
status = "disabled";
};
&i2c2 {
status = "disabled";
};
&gpt3 {
status = "disabled";
};
&gpt4 {
status = "disabled";
};
&ocram {
reg = <0x00901000 0xf000>;
};
&reg_can2_3v3 {
status = "disabled";
};
&rpmsg{
vdev-nums = <1>;
reg = <0xbfff0000 0x10000>;
status = "okay";
};
&uart2 {
status = "disabled";
};
&wdog3{
status = "disabled";
};

31
arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts 100644
View File

@ -0,0 +1,31 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx7d-sdb.dts"
/ {
mipi_dsi_reset: mipi-dsi-reset {
compatible = "gpio-reset";
reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
#reset-cells = <0>;
};
};
&lcdif {
disp-dev = "mipi_dsi_samsung";
disp-videomode = "TRUULY-WVGA-SYNC-LOW";
};
&mipi_dsi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mipi_dsi_reset>;
lcd_panel = "TRULY-WVGA-TFT3P5581E";
resets = <&mipi_dsi_reset>;
status = "okay";
};

9
arch/arm/boot/dts/imx7d-sdb-qspi.dts 100644
View File

@ -0,0 +1,9 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx7d-sdb.dts"
#include "imx7d-sdb-qspi.dtsi"

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