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drm/amdgpu: add kernel doc for memory domains. 

Document the GEM domains exposed to userspace.

Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hifive-unleashed-5.1
Samuel Li 2018-05-24 14:32:49 -04:00 committed by Alex Deucher
parent 6f4e8d6e59
commit b646c1dc83
1 changed files with 23 additions and 0 deletions
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23
include/uapi/drm/amdgpu_drm.h
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@ -72,6 +72,29 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
/**
* DOC: memory domains
*
* %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
* Memory in this pool could be swapped out to disk if there is pressure.
*
* %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
* GPU's virtual address space via gart. Gart memory linearizes non-contiguous
* pages of system memory, allows GPU access system memory in a linezrized
* fashion.
*
* %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
* carved out by the BIOS.
*
* %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
* across shader threads.
*
* %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the
* execution of all the waves on a device.
*
* %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
* for appending data.
*/
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
#define AMDGPU_GEM_DOMAIN_VRAM 0x4