Merge branch 'for-linus' into for-next
This commit is contained in:
Bartlomiej Zolnierkiewicz
commit
b656eba122
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@ -2743,7 +2743,7 @@ IDE SUBSYSTEM
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P: Bartlomiej Zolnierkiewicz
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M: bzolnier@gmail.com
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L: linux-ide@vger.kernel.org
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T: quilt kernel.org/pub/linux/kernel/people/bart/pata-2.6/
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6.git
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S: Maintained
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F: Documentation/ide/
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F: drivers/ide/
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@ -42,16 +42,9 @@
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#define BK3710_BMICP 0x00
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#define BK3710_BMISP 0x02
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#define BK3710_BMIDTP 0x04
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#define BK3710_BMICS 0x08
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#define BK3710_BMISS 0x0A
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#define BK3710_BMIDTS 0x0C
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#define BK3710_IDETIMP 0x40
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#define BK3710_IDETIMS 0x42
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#define BK3710_SIDETIM 0x44
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#define BK3710_SLEWCTL 0x45
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#define BK3710_IDESTATUS 0x47
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#define BK3710_UDMACTL 0x48
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#define BK3710_UDMATIM 0x4A
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#define BK3710_MISCCTL 0x50
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#define BK3710_REGSTB 0x54
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#define BK3710_REGRCVR 0x58
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@ -63,7 +56,6 @@
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#define BK3710_UDMATRP 0x70
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#define BK3710_UDMAENV 0x74
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#define BK3710_IORDYTMP 0x78
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#define BK3710_IORDYTMS 0x7C
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static unsigned ideclk_period; /* in nanoseconds */
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@ -74,12 +66,12 @@ struct palm_bk3710_udmatiming {
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};
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static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = {
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{160, 240 / 2,}, /* UDMA Mode 0 */
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{125, 160 / 2,}, /* UDMA Mode 1 */
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{100, 120 / 2,}, /* UDMA Mode 2 */
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{100, 90 / 2,}, /* UDMA Mode 3 */
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{100, 60 / 2,}, /* UDMA Mode 4 */
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{85, 40 / 2,}, /* UDMA Mode 5 */
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{ 160, 240 / 2 }, /* UDMA Mode 0 */
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{ 125, 160 / 2 }, /* UDMA Mode 1 */
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{ 100, 120 / 2 }, /* UDMA Mode 2 */
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{ 100, 90 / 2 }, /* UDMA Mode 3 */
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{ 100, 60 / 2 }, /* UDMA Mode 4 */
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{ 85, 40 / 2 }, /* UDMA Mode 5 */
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};
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static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
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@ -96,11 +88,6 @@ static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
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trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime,
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ideclk_period) - 1;
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/* udmatim Register */
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val16 = readw(base + BK3710_UDMATIM) & (dev ? 0xFF0F : 0xFFF0);
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val16 |= (mode << (dev ? 4 : 0));
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writew(val16, base + BK3710_UDMATIM);
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/* udmastb Ultra DMA Access Strobe Width */
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val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
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val32 |= (t0 << (dev ? 8 : 0));
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@ -161,10 +148,11 @@ static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
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u32 val32;
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struct ide_timing *t;
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t = ide_timing_find_mode(XFER_PIO_0 + mode);
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/* PIO Data Setup */
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t0 = DIV_ROUND_UP(cycletime, ideclk_period);
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t2 = DIV_ROUND_UP(ide_timing_find_mode(XFER_PIO_0 + mode)->active,
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ideclk_period);
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t2 = DIV_ROUND_UP(t->active, ideclk_period);
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t2i = t0 - t2 - 1;
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t2 -= 1;
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@ -185,7 +173,6 @@ static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
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}
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/* TASKFILE Setup */
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t = ide_timing_find_mode(XFER_PIO_0 + mode);
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t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
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t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
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@ -234,42 +221,23 @@ static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio)
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static void __devinit palm_bk3710_chipinit(void __iomem *base)
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{
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/*
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* enable the reset_en of ATA controller so that when ata signals
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* are brought out, by writing into device config. at that
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* time por_n signal should not be 'Z' and have a stable value.
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* REVISIT: the ATA reset signal needs to be managed through a
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* GPIO, which means it should come from platform_data. Until
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* we get and use such information, we have to trust that things
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* have been reset before we get here.
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*/
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writel(0x0300, base + BK3710_MISCCTL);
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/* wait for some time and deassert the reset of ATA Device. */
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mdelay(100);
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/* Deassert the Reset */
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writel(0x0200, base + BK3710_MISCCTL);
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/*
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* Program the IDETIMP Register Value based on the following assumptions
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*
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* (ATA_IDETIMP_IDEEN , ENABLE ) |
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* (ATA_IDETIMP_SLVTIMEN , DISABLE) |
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* (ATA_IDETIMP_RDYSMPL , 70NS) |
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* (ATA_IDETIMP_RDYRCVRY , 50NS) |
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* (ATA_IDETIMP_DMAFTIM1 , PIOCOMP) |
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* (ATA_IDETIMP_PREPOST1 , DISABLE) |
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* (ATA_IDETIMP_RDYSEN1 , DISABLE) |
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* (ATA_IDETIMP_PIOFTIM1 , DISABLE) |
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* (ATA_IDETIMP_DMAFTIM0 , PIOCOMP) |
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* (ATA_IDETIMP_PREPOST0 , DISABLE) |
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* (ATA_IDETIMP_RDYSEN0 , DISABLE) |
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* (ATA_IDETIMP_PIOFTIM0 , DISABLE)
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*
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* DM6446 silicon rev 2.1 and earlier have no observed net benefit
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* from enabling prefetch/postwrite.
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*/
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writew(0xB388, base + BK3710_IDETIMP);
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/*
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* Configure SIDETIM Register
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* (ATA_SIDETIM_RDYSMPS1 ,120NS ) |
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* (ATA_SIDETIM_RDYRCYS1 ,120NS )
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*/
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writeb(0, base + BK3710_SIDETIM);
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writew(BIT(15), base + BK3710_IDETIMP);
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/*
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* UDMACTL Ultra-ATA DMA Control
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@ -281,11 +249,11 @@ static void __devinit palm_bk3710_chipinit(void __iomem *base)
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/*
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* MISCCTL Miscellaneous Conrol Register
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* (ATA_MISCCTL_RSTMODEP , 1) |
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* (ATA_MISCCTL_RESETP , 0) |
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* (ATA_MISCCTL_HWNHLD1P , 1 cycle)
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* (ATA_MISCCTL_HWNHLD0P , 1 cycle)
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* (ATA_MISCCTL_TIMORIDE , 1)
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*/
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writel(0x201, base + BK3710_MISCCTL);
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writel(0x001, base + BK3710_MISCCTL);
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/*
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* IORDYTMP IORDY Timer for Primary Register
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@ -355,10 +323,9 @@ static int __init palm_bk3710_probe(struct platform_device *pdev)
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clk_enable(clk);
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rate = clk_get_rate(clk);
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ideclk_period = 1000000000UL / rate;
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/* Register the IDE interface with Linux ATA Interface */
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memset(&hw, 0, sizeof(hw));
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/* NOTE: round *down* to meet minimum timings; we count in clocks */
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ideclk_period = 1000000000UL / rate;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (mem == NULL) {
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@ -388,6 +355,7 @@ static int __init palm_bk3710_probe(struct platform_device *pdev)
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/* Configure the Palm Chip controller */
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palm_bk3710_chipinit(base);
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memset(&hw, 0, sizeof(hw));
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for (i = 0; i < IDE_NR_PORTS - 2; i++)
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hw.io_ports_array[i] = (unsigned long)
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(base + IDE_PALM_ATA_PRI_REG_OFFSET + i);
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@ -400,6 +368,7 @@ static int __init palm_bk3710_probe(struct platform_device *pdev)
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palm_bk3710_port_info.udma_mask = rate < 100000000 ? ATA_UDMA4 :
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ATA_UDMA5;
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/* Register the IDE interface with Linux */
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rc = ide_host_add(&palm_bk3710_port_info, hws, NULL);
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if (rc)
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goto out;
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