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clk: meson: mpll: correct N2 maximum value 

Gxbb datasheet says N2 maximum value is 127 but the register field is
9 bits wide, the maximum value should 511.

Test shows value greater than 127, all the way to 511, works well

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20170309104154.28295-9-jbrunet@baylibre.com
hifive-unleashed-5.1
Jerome Brunet 2017-03-09 11:41:53 +01:00 committed by Michael Turquette
parent b778f7451a
commit b68fb7871e
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/meson/clk-mpll.c
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@ -68,7 +68,7 @@
#define SDM_MIN 1
#define SDM_MAX 16383
#define N2_MIN 4
#define N2_MAX 127
#define N2_MAX 511
#define to_meson_clk_mpll(_hw) container_of(_hw, struct meson_clk_mpll, hw)