sh: pci: Support secondary FPGA-driven PCIe clocks on SDK7786.
The SDK7786 FPGA has secondary control over the PCIe clocks, specifically relating to the slots and oscillator. This ties the FPGA clocks in to the clock framework and balances the refcounting similar to how the primary on-chip clocks are managed. While the on-chip clocks are per-port, the FPGA clock enable/disable is global for the entire block. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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61a46766c9
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@ -20,6 +20,8 @@
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#include <asm/machvec.h>
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#include <asm/machvec.h>
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#include <asm/heartbeat.h>
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#include <asm/heartbeat.h>
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#include <asm/sizes.h>
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#include <asm/sizes.h>
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#include <asm/clock.h>
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#include <asm/clkdev.h>
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#include <asm/reboot.h>
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#include <asm/reboot.h>
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#include <asm/smp-ops.h>
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#include <asm/smp-ops.h>
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@ -140,6 +142,45 @@ static int sdk7786_mode_pins(void)
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return fpga_read_reg(MODSWR);
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return fpga_read_reg(MODSWR);
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}
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}
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/*
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* FPGA-driven PCIe clocks
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*
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* Historically these include the oscillator, clock B (slots 2/3/4) and
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* clock A (slot 1 and the CPU clock). Newer revs of the PCB shove
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* everything under a single PCIe clocks enable bit that happens to map
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* to the same bit position as the oscillator bit for earlier FPGA
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* versions.
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*
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* Given that the legacy clocks have the side-effect of shutting the CPU
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* off through the FPGA along with the PCI slots, we simply leave them in
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* their initial state and don't bother registering them with the clock
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* framework.
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*/
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static int sdk7786_pcie_clk_enable(struct clk *clk)
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{
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fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR);
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return 0;
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}
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static void sdk7786_pcie_clk_disable(struct clk *clk)
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{
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fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
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}
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static struct clk_ops sdk7786_pcie_clk_ops = {
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.enable = sdk7786_pcie_clk_enable,
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.disable = sdk7786_pcie_clk_disable,
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};
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static struct clk sdk7786_pcie_clk = {
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.ops = &sdk7786_pcie_clk_ops,
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};
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static struct clk_lookup sdk7786_pcie_cl = {
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.con_id = "pcie_plat_clk",
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.clk = &sdk7786_pcie_clk,
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};
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static int sdk7786_clk_init(void)
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static int sdk7786_clk_init(void)
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{
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{
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struct clk *clk;
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struct clk *clk;
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@ -158,7 +199,18 @@ static int sdk7786_clk_init(void)
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ret = clk_set_rate(clk, 33333333);
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ret = clk_set_rate(clk, 33333333);
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clk_put(clk);
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clk_put(clk);
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return ret;
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/*
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* Setup the FPGA clocks.
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*/
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ret = clk_register(&sdk7786_pcie_clk);
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if (unlikely(ret)) {
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pr_err("FPGA clock registration failed\n");
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return ret;
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}
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clkdev_add(&sdk7786_pcie_cl);
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return 0;
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}
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}
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static void sdk7786_restart(char *cmd)
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static void sdk7786_restart(char *cmd)
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@ -10,7 +10,6 @@
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#define pr_fmt(fmt) "PCI: " fmt
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#define pr_fmt(fmt) "PCI: " fmt
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/pci.h>
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#include <mach/fpga.h>
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#include <mach/fpga.h>
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@ -17,7 +17,6 @@
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#include <linux/sh_clk.h>
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#include <linux/sh_clk.h>
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#include "pcie-sh7786.h"
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#include "pcie-sh7786.h"
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#include <asm/sizes.h>
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#include <asm/sizes.h>
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#include <asm/clock.h>
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struct sh7786_pcie_port {
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struct sh7786_pcie_port {
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struct pci_channel *hose;
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struct pci_channel *hose;
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@ -510,6 +509,7 @@ static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
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static int __init sh7786_pcie_init(void)
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static int __init sh7786_pcie_init(void)
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{
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{
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struct clk *platclk;
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int ret = 0, i;
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int ret = 0, i;
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printk(KERN_NOTICE "PCI: Starting initialization.\n");
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printk(KERN_NOTICE "PCI: Starting initialization.\n");
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@ -527,6 +527,22 @@ static int __init sh7786_pcie_init(void)
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if (unlikely(!sh7786_pcie_ports))
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if (unlikely(!sh7786_pcie_ports))
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return -ENOMEM;
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return -ENOMEM;
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/*
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* Fetch any optional platform clock associated with this block.
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*
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* This is a rather nasty hack for boards with spec-mocking FPGAs
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* that have a secondary set of clocks outside of the on-chip
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* ones that need to be accounted for before there is any chance
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* of touching the existing MSTP bits or CPG clocks.
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*/
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platclk = clk_get(NULL, "pcie_plat_clk");
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if (IS_ERR(platclk)) {
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/* Sane hardware should probably get a WARN_ON.. */
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platclk = NULL;
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}
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clk_enable(platclk);
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printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
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printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
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for (i = 0; i < nr_ports; i++) {
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for (i = 0; i < nr_ports; i++) {
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@ -539,8 +555,11 @@ static int __init sh7786_pcie_init(void)
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ret |= sh7786_pcie_hwops->port_init_hw(port);
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ret |= sh7786_pcie_hwops->port_init_hw(port);
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}
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}
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if (unlikely(ret))
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if (unlikely(ret)) {
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clk_disable(platclk);
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clk_put(platclk);
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return ret;
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return ret;
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}
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return 0;
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return 0;
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}
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}
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@ -39,7 +39,7 @@
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#define PCIECR_PRST3 BIT(11) /* slot 3 card present */
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#define PCIECR_PRST3 BIT(11) /* slot 3 card present */
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#define PCIECR_PRST2 BIT(10) /* slot 2 card present */
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#define PCIECR_PRST2 BIT(10) /* slot 2 card present */
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#define PCIECR_PRST1 BIT(9) /* slot 1 card present */
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#define PCIECR_PRST1 BIT(9) /* slot 1 card present */
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#define PCIECR_CLKEN BIT(4)
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#define PCIECR_CLKEN BIT(4) /* oscillator enable */
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#define FAER 0x150
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#define FAER 0x150
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#define USRGPIR 0x160
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#define USRGPIR 0x160
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