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arm64: dts: uniphier: add eMMC hardware reset provider node 

Add mmc-pwrseq-emmc node to perform standard eMMC hardware reset
procedure.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
hifive-unleashed-5.1
Masahiro Yamada 2017-10-24 00:21:37 +09:00
parent 15e85695e5
commit b6e5ec203b
3 changed files with 23 additions and 0 deletions
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8
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
View File

@ -7,6 +7,8 @@
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/gpio/gpio.h>
/memreserve/ 0x80000000 0x02000000;
/ {
@ -96,6 +98,11 @@
};
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>,
@ -310,6 +317,7 @@
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;

7
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
View File

@ -7,6 +7,7 @@
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/thermal/thermal.h>
/memreserve/ 0x80000000 0x02000000;
@ -169,6 +170,11 @@
};
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>,
@ -416,6 +422,7 @@
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;

8
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
View File

@ -7,6 +7,8 @@
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/gpio/gpio.h>
/memreserve/ 0x80000000 0x02000000;
/ {
@ -124,6 +126,11 @@
};
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>,
@ -317,6 +324,7 @@
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;