i2c-omap: FIFO handling support and broken hw workaround for i2c-omap
Based on an earlier patch from Nishant Menon: - Transfers can use FIFO on FIFO capable devices - Prevents errors for HSI2C if FIFO is not used - Implemented errenous handling of STT-STP handling on SDP2430 Also merged in is a fix from Jaron Marini to fix occasional i2c hang if OMAP_I2C_CON_STT remains asserted. Signed-off-by: Jason P Marini <jason.marini@gmail.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Nishanth Menon
Tony Lindgren
parent
4574eb6892
commit
b6ee52c399
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@ -55,8 +55,11 @@
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#define OMAP_I2C_SCLL_REG 0x34
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#define OMAP_I2C_SCLH_REG 0x38
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#define OMAP_I2C_SYSTEST_REG 0x3c
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#define OMAP_I2C_BUFSTAT_REG 0x40
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/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
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#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
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#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
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#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
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#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
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#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
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@ -64,7 +67,8 @@
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#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
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/* I2C Status Register (OMAP_I2C_STAT): */
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#define OMAP_I2C_STAT_SBD (1 << 15) /* Single byte data */
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#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
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#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
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#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
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#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
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#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
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@ -78,12 +82,14 @@
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/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
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#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
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#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
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#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
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#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
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/* I2C Configuration Register (OMAP_I2C_CON): */
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#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
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#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
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#define OMAP_I2C_CON_OPMODE (1 << 12) /* High Speed support */
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#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
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#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
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#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
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#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
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@ -127,7 +133,12 @@ struct omap_i2c_dev {
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u8 *buf;
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size_t buf_len;
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struct i2c_adapter adapter;
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u8 fifo_size; /* use as flag and value
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* fifo_size==0 implies no fifo
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* if set, should be trsh+1
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*/
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unsigned rev1:1;
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unsigned b_hw:1; /* bad h/w fixes */
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unsigned idle:1;
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u16 iestate; /* Saved interrupt register */
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};
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@ -297,6 +308,14 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
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omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
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omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
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if (dev->fifo_size)
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/* Note: setup required fifo size - 1 */
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omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
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(dev->fifo_size - 1) << 8 | /* RTRSH */
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OMAP_I2C_BUF_RXFIF_CLR |
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(dev->fifo_size - 1) | /* XTRSH */
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OMAP_I2C_BUF_TXFIF_CLR);
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/* Take the I2C module out of reset: */
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
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@ -304,7 +323,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
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omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
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(OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
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OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
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OMAP_I2C_IE_AL));
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OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
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(OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
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return 0;
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}
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@ -351,6 +371,11 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
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omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
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/* Clear the FIFO Buffers */
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w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
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w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
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omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
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init_completion(&dev->cmd_complete);
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dev->cmd_err = 0;
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@ -358,16 +383,39 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
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/* High speed configuration */
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if (dev->speed > 400)
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w |= OMAP_I2C_CON_OPMODE;
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w |= OMAP_I2C_CON_OPMODE_HS;
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if (msg->flags & I2C_M_TEN)
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w |= OMAP_I2C_CON_XA;
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if (!(msg->flags & I2C_M_RD))
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w |= OMAP_I2C_CON_TRX;
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if (stop)
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if (!dev->b_hw && stop)
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w |= OMAP_I2C_CON_STP;
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
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/*
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* Don't write stt and stp together on some hardware.
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*/
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if (dev->b_hw && stop) {
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unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
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u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
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while (con & OMAP_I2C_CON_STT) {
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con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
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/* Let the user know if i2c is in a bad state */
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if (time_after(jiffies, delay)) {
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dev_err(dev->dev, "controller timed out "
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"waiting for start condition to finish\n");
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return -ETIMEDOUT;
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}
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cpu_relax();
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}
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w |= OMAP_I2C_CON_STP;
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w &= ~OMAP_I2C_CON_STT;
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
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}
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/*
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* REVISIT: We should abort the transfer on signals, but the bus goes
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* into arbitration and we're currently unable to recover from it.
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@ -516,7 +564,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
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struct omap_i2c_dev *dev = dev_id;
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u16 bits;
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u16 stat, w;
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int count = 0;
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int err, count = 0;
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if (dev->idle)
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return IRQ_NONE;
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@ -531,39 +579,94 @@ omap_i2c_isr(int this_irq, void *dev_id)
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omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
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if (stat & OMAP_I2C_STAT_ARDY) {
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omap_i2c_complete_cmd(dev, 0);
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err = 0;
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if (stat & OMAP_I2C_STAT_NACK) {
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err |= OMAP_I2C_STAT_NACK;
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
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OMAP_I2C_CON_STP);
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}
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if (stat & OMAP_I2C_STAT_AL) {
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dev_err(dev->dev, "Arbitration lost\n");
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err |= OMAP_I2C_STAT_AL;
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}
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if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
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OMAP_I2C_STAT_AL))
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omap_i2c_complete_cmd(dev, err);
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if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
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u8 num_bytes = 1;
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if (dev->fifo_size) {
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if (stat & OMAP_I2C_STAT_RRDY)
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num_bytes = dev->fifo_size;
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else
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num_bytes = omap_i2c_read_reg(dev,
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OMAP_I2C_BUFSTAT_REG);
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}
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while (num_bytes) {
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num_bytes--;
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w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
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if (dev->buf_len) {
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*dev->buf++ = w;
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dev->buf_len--;
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/* Data reg from 2430 is 8 bit wide */
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if (!cpu_is_omap2430()) {
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if (dev->buf_len) {
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*dev->buf++ = w >> 8;
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dev->buf_len--;
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}
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}
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} else {
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if (stat & OMAP_I2C_STAT_RRDY)
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dev_err(dev->dev,
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"RRDY IRQ while no data"
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" requested\n");
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if (stat & OMAP_I2C_STAT_RDR)
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dev_err(dev->dev,
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"RDR IRQ while no data"
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" requested\n");
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break;
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}
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}
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omap_i2c_ack_stat(dev,
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stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
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continue;
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}
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if (stat & OMAP_I2C_STAT_RRDY) {
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w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
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if (dev->buf_len) {
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*dev->buf++ = w;
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dev->buf_len--;
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if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
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u8 num_bytes = 1;
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if (dev->fifo_size) {
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if (stat & OMAP_I2C_STAT_XRDY)
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num_bytes = dev->fifo_size;
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else
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num_bytes = omap_i2c_read_reg(dev,
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OMAP_I2C_BUFSTAT_REG);
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}
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while (num_bytes) {
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num_bytes--;
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w = 0;
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if (dev->buf_len) {
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*dev->buf++ = w >> 8;
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w = *dev->buf++;
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dev->buf_len--;
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/* Data reg from 2430 is 8 bit wide */
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if (!cpu_is_omap2430()) {
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if (dev->buf_len) {
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w |= *dev->buf++ << 8;
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dev->buf_len--;
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}
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}
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} else {
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if (stat & OMAP_I2C_STAT_XRDY)
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dev_err(dev->dev,
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"XRDY IRQ while no "
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"data to send\n");
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if (stat & OMAP_I2C_STAT_XDR)
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dev_err(dev->dev,
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"XDR IRQ while no "
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"data to send\n");
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break;
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}
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} else
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dev_err(dev->dev, "RRDY IRQ while no data "
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"requested\n");
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omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
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continue;
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}
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if (stat & OMAP_I2C_STAT_XRDY) {
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w = 0;
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if (dev->buf_len) {
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w = *dev->buf++;
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dev->buf_len--;
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if (dev->buf_len) {
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w |= *dev->buf++ << 8;
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dev->buf_len--;
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}
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} else
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dev_err(dev->dev, "XRDY IRQ while no "
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"data to send\n");
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omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
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omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
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omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
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}
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omap_i2c_ack_stat(dev,
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stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
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continue;
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}
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if (stat & OMAP_I2C_STAT_ROVR) {
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@ -571,18 +674,9 @@ omap_i2c_isr(int this_irq, void *dev_id)
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dev->cmd_err |= OMAP_I2C_STAT_ROVR;
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}
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if (stat & OMAP_I2C_STAT_XUDF) {
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dev_err(dev->dev, "Transmit overflow\n");
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dev_err(dev->dev, "Transmit underflow\n");
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dev->cmd_err |= OMAP_I2C_STAT_XUDF;
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}
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if (stat & OMAP_I2C_STAT_NACK) {
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omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
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OMAP_I2C_CON_STP);
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}
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if (stat & OMAP_I2C_STAT_AL) {
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dev_err(dev->dev, "Arbitration lost\n");
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omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
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}
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}
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return count ? IRQ_HANDLED : IRQ_NONE;
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@ -651,6 +745,22 @@ omap_i2c_probe(struct platform_device *pdev)
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if (cpu_is_omap15xx())
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dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
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if (cpu_is_omap2430()) {
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u16 s;
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/* Set up the fifo size - Get total size */
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s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
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dev->fifo_size = 0x8 << s;
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/*
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* Set up notification threshold as half the total available
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* size. This is to ensure that we can handle the status on int
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* call back latencies.
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*/
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dev->fifo_size = (dev->fifo_size / 2);
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dev->b_hw = 1; /* Enable hardware fixes */
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}
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/* reset ASAP, clearing any IRQs */
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omap_i2c_init(dev);
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