ARM: dts: add sysmmu nodes for exynos5420
This patch adds System MMU nodes to all defined devices that are specific to Exynos5420/5800/5422 series. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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@ -179,6 +179,8 @@
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clocks = <&clock CLK_MFC>;
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clock-names = "mfc";
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power-domains = <&mfc_pd>;
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iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
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iommu-names = "left", "right";
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};
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mmc_0: mmc@12200000 {
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@ -713,6 +715,7 @@
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<&clock CLK_SCLK_HDMI>;
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clock-names = "mixer", "hdmi", "sclk_hdmi";
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power-domains = <&disp_pd>;
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iommus = <&sysmmu_tv>;
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};
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gsc_0: video-scaler@13e00000 {
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@ -722,6 +725,7 @@
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clocks = <&clock CLK_GSCL0>;
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clock-names = "gscl";
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power-domains = <&gsc_pd>;
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iommus = <&sysmmu_gscl0>;
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};
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gsc_1: video-scaler@13e10000 {
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@ -731,6 +735,7 @@
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clocks = <&clock CLK_GSCL1>;
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clock-names = "gscl";
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power-domains = <&gsc_pd>;
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iommus = <&sysmmu_gscl1>;
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};
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jpeg_0: jpeg@11F50000 {
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@ -739,6 +744,7 @@
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interrupts = <0 89 0>;
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clock-names = "jpeg";
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clocks = <&clock CLK_JPEG>;
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iommus = <&sysmmu_jpeg0>;
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};
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jpeg_1: jpeg@11F60000 {
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@ -747,6 +753,7 @@
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interrupts = <0 168 0>;
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clock-names = "jpeg";
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clocks = <&clock CLK_JPEG2>;
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iommus = <&sysmmu_jpeg1>;
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};
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pmu_system_controller: system-controller@10040000 {
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@ -941,6 +948,180 @@
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samsung,sysreg-phandle = <&sysreg_system_controller>;
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samsung,pmureg-phandle = <&pmu_system_controller>;
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};
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sysmmu_g2dr: sysmmu@0x10A60000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x10A60000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <24 5>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
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#iommu-cells = <0>;
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};
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sysmmu_g2dw: sysmmu@0x10A70000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x10A70000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <22 2>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
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#iommu-cells = <0>;
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};
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sysmmu_tv: sysmmu@0x14650000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x14650000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <7 4>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
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power-domains = <&disp_pd>;
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#iommu-cells = <0>;
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};
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sysmmu_gscl0: sysmmu@0x13E80000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13E80000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <2 0>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
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power-domains = <&gsc_pd>;
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#iommu-cells = <0>;
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};
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sysmmu_gscl1: sysmmu@0x13E90000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13E90000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <2 2>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
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power-domains = <&gsc_pd>;
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#iommu-cells = <0>;
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};
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sysmmu_scaler0r: sysmmu@0x12880000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x12880000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <22 4>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
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#iommu-cells = <0>;
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};
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sysmmu_scaler1r: sysmmu@0x12890000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x12890000 0x1000>;
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interrupts = <0 186 0>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
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#iommu-cells = <0>;
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};
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sysmmu_scaler2r: sysmmu@0x128A0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x128A0000 0x1000>;
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interrupts = <0 188 0>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
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#iommu-cells = <0>;
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};
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sysmmu_scaler0w: sysmmu@0x128C0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x128C0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <27 2>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
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#iommu-cells = <0>;
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};
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sysmmu_scaler1w: sysmmu@0x128D0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x128D0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <22 6>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
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#iommu-cells = <0>;
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};
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sysmmu_scaler2w: sysmmu@0x128E0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x128E0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <19 6>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
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#iommu-cells = <0>;
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};
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sysmmu_jpeg0: sysmmu@0x11F10000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x11F10000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <4 2>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
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#iommu-cells = <0>;
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};
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sysmmu_jpeg1: sysmmu@0x11F20000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x11F20000 0x1000>;
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interrupts = <0 169 0>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
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#iommu-cells = <0>;
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};
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sysmmu_mfc_l: sysmmu@0x11200000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x11200000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <6 2>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
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power-domains = <&mfc_pd>;
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#iommu-cells = <0>;
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};
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sysmmu_mfc_r: sysmmu@0x11210000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x11210000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <8 5>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
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power-domains = <&mfc_pd>;
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#iommu-cells = <0>;
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};
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sysmmu_fimd1_0: sysmmu@0x14640000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x14640000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <3 2>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
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power-domains = <&disp_pd>;
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#iommu-cells = <0>;
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};
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sysmmu_fimd1_1: sysmmu@0x14680000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x14680000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <3 0>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
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power-domains = <&disp_pd>;
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#iommu-cells = <0>;
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};
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};
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&dp {
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@ -955,6 +1136,8 @@
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clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
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clock-names = "sclk_fimd", "fimd";
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power-domains = <&disp_pd>;
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iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
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iommu-names = "m0", "m1";
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};
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&rtc {
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