perf, x86: Implement IBS initialization
This patch implements IBS feature detection and initialzation. The code is shared between perf and oprofile. If IBS is available on the system for perf, a pmu is setup. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1316597423-25723-3-git-send-email-robert.richter@amd.com Signed-off-by: Ingo Molnar <mingo@elte.hu>hifive-unleashed-5.1
Robert Richter
Ingo Molnar
parent
ee5789dbcc
commit
b716916679
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@ -159,6 +159,8 @@ union cpuid10_edx {
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#define IBS_OP_MAX_CNT 0x0000FFFFULL
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#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
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extern u32 get_ibs_caps(void);
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#ifdef CONFIG_PERF_EVENTS
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extern void perf_events_lapic_init(void);
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@ -36,7 +36,7 @@ endif
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obj-$(CONFIG_X86_MCE) += mcheck/
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obj-$(CONFIG_MTRR) += mtrr/
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obj-$(CONFIG_X86_LOCAL_APIC) += perfctr-watchdog.o
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obj-$(CONFIG_X86_LOCAL_APIC) += perfctr-watchdog.o perf_event_amd_ibs.o
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quiet_cmd_mkcapflags = MKCAP $@
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cmd_mkcapflags = $(PERL) $(srctree)/$(src)/mkcapflags.pl $< $@
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@ -0,0 +1,294 @@
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/*
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* Performance events - AMD IBS
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
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*
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* For licencing details see kernel-base/COPYING
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*/
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#include <linux/perf_event.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <asm/apic.h>
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static u32 ibs_caps;
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#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
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static struct pmu perf_ibs;
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static int perf_ibs_init(struct perf_event *event)
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{
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if (perf_ibs.type != event->attr.type)
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return -ENOENT;
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return 0;
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}
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static int perf_ibs_add(struct perf_event *event, int flags)
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{
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return 0;
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}
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static void perf_ibs_del(struct perf_event *event, int flags)
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{
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}
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static struct pmu perf_ibs = {
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.event_init= perf_ibs_init,
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.add= perf_ibs_add,
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.del= perf_ibs_del,
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};
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static __init int perf_event_ibs_init(void)
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{
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if (!ibs_caps)
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return -ENODEV; /* ibs not supported by the cpu */
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perf_pmu_register(&perf_ibs, "ibs", -1);
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printk(KERN_INFO "perf: AMD IBS detected (0x%08x)\n", ibs_caps);
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return 0;
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}
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#else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
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static __init int perf_event_ibs_init(void) { return 0; }
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#endif
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/* IBS - apic initialization, for perf and oprofile */
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static __init u32 __get_ibs_caps(void)
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{
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u32 caps;
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unsigned int max_level;
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if (!boot_cpu_has(X86_FEATURE_IBS))
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return 0;
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/* check IBS cpuid feature flags */
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max_level = cpuid_eax(0x80000000);
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if (max_level < IBS_CPUID_FEATURES)
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return IBS_CAPS_DEFAULT;
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caps = cpuid_eax(IBS_CPUID_FEATURES);
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if (!(caps & IBS_CAPS_AVAIL))
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/* cpuid flags not valid */
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return IBS_CAPS_DEFAULT;
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return caps;
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}
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u32 get_ibs_caps(void)
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{
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return ibs_caps;
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}
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EXPORT_SYMBOL(get_ibs_caps);
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static inline int get_eilvt(int offset)
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{
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return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
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}
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static inline int put_eilvt(int offset)
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{
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return !setup_APIC_eilvt(offset, 0, 0, 1);
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}
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/*
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* Check and reserve APIC extended interrupt LVT offset for IBS if available.
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*/
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static inline int ibs_eilvt_valid(void)
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{
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int offset;
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u64 val;
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int valid = 0;
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preempt_disable();
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rdmsrl(MSR_AMD64_IBSCTL, val);
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offset = val & IBSCTL_LVT_OFFSET_MASK;
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if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
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pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
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smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
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goto out;
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}
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if (!get_eilvt(offset)) {
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pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
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smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
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goto out;
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}
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valid = 1;
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out:
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preempt_enable();
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return valid;
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}
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static int setup_ibs_ctl(int ibs_eilvt_off)
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{
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struct pci_dev *cpu_cfg;
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int nodes;
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u32 value = 0;
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nodes = 0;
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cpu_cfg = NULL;
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do {
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cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
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PCI_DEVICE_ID_AMD_10H_NB_MISC,
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cpu_cfg);
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if (!cpu_cfg)
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break;
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++nodes;
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pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
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| IBSCTL_LVT_OFFSET_VALID);
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pci_read_config_dword(cpu_cfg, IBSCTL, &value);
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if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
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pci_dev_put(cpu_cfg);
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printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
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"IBSCTL = 0x%08x\n", value);
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return -EINVAL;
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}
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} while (1);
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if (!nodes) {
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printk(KERN_DEBUG "No CPU node configured for IBS\n");
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return -ENODEV;
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}
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return 0;
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}
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/*
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* This runs only on the current cpu. We try to find an LVT offset and
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* setup the local APIC. For this we must disable preemption. On
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* success we initialize all nodes with this offset. This updates then
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* the offset in the IBS_CTL per-node msr. The per-core APIC setup of
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* the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
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* is using the new offset.
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*/
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static int force_ibs_eilvt_setup(void)
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{
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int offset;
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int ret;
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preempt_disable();
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/* find the next free available EILVT entry, skip offset 0 */
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for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
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if (get_eilvt(offset))
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break;
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}
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preempt_enable();
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if (offset == APIC_EILVT_NR_MAX) {
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printk(KERN_DEBUG "No EILVT entry available\n");
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return -EBUSY;
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}
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ret = setup_ibs_ctl(offset);
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if (ret)
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goto out;
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if (!ibs_eilvt_valid()) {
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ret = -EFAULT;
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goto out;
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}
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pr_err(FW_BUG "using offset %d for IBS interrupts\n", offset);
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pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");
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return 0;
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out:
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preempt_disable();
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put_eilvt(offset);
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preempt_enable();
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return ret;
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}
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static inline int get_ibs_lvt_offset(void)
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{
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u64 val;
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rdmsrl(MSR_AMD64_IBSCTL, val);
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if (!(val & IBSCTL_LVT_OFFSET_VALID))
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return -EINVAL;
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return val & IBSCTL_LVT_OFFSET_MASK;
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}
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static void setup_APIC_ibs(void *dummy)
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{
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int offset;
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offset = get_ibs_lvt_offset();
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if (offset < 0)
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goto failed;
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if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
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return;
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failed:
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pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
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smp_processor_id());
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}
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static void clear_APIC_ibs(void *dummy)
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{
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int offset;
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offset = get_ibs_lvt_offset();
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if (offset >= 0)
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setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
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}
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static int __cpuinit
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perf_ibs_cpu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
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{
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switch (action & ~CPU_TASKS_FROZEN) {
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case CPU_STARTING:
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setup_APIC_ibs(NULL);
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break;
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case CPU_DYING:
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clear_APIC_ibs(NULL);
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break;
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default:
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break;
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}
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return NOTIFY_OK;
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}
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static __init int amd_ibs_init(void)
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{
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u32 caps;
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int ret;
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caps = __get_ibs_caps();
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if (!caps)
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return -ENODEV; /* ibs not supported by the cpu */
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if (!ibs_eilvt_valid()) {
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ret = force_ibs_eilvt_setup();
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if (ret) {
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pr_err("Failed to setup IBS, %d\n", ret);
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return ret;
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}
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}
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get_online_cpus();
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ibs_caps = caps;
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/* make ibs_caps visible to other cpus: */
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smp_mb();
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perf_cpu_notifier(perf_ibs_cpu_notifier);
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smp_call_function(setup_APIC_ibs, NULL, 1);
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put_online_cpus();
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return perf_event_ibs_init();
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}
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/* Since we need the pci subsystem to init ibs we can't do this earlier: */
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device_initcall(amd_ibs_init);
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@ -385,8 +385,6 @@ static void nmi_cpu_shutdown(void *dummy)
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apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
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apic_write(APIC_LVTERR, v);
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nmi_cpu_restore_registers(msrs);
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if (model->cpu_down)
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model->cpu_down();
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}
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static void nmi_cpu_up(void *dummy)
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@ -74,27 +74,6 @@ static struct ibs_state ibs_state;
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#define IBS_RANDOM_MASK ((1ULL << IBS_RANDOM_BITS) - 1)
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#define IBS_RANDOM_MAXCNT_OFFSET (1ULL << (IBS_RANDOM_BITS - 5))
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static u32 get_ibs_caps(void)
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{
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u32 ibs_caps;
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unsigned int max_level;
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if (!boot_cpu_has(X86_FEATURE_IBS))
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return 0;
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/* check IBS cpuid feature flags */
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max_level = cpuid_eax(0x80000000);
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if (max_level < IBS_CPUID_FEATURES)
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return IBS_CAPS_DEFAULT;
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ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
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if (!(ibs_caps & IBS_CAPS_AVAIL))
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/* cpuid flags not valid */
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return IBS_CAPS_DEFAULT;
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return ibs_caps;
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}
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/*
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* 16-bit Linear Feedback Shift Register (LFSR)
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*
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@ -285,81 +264,6 @@ static void op_amd_stop_ibs(void)
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wrmsrl(MSR_AMD64_IBSOPCTL, 0);
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}
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static inline int get_eilvt(int offset)
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{
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return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
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}
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static inline int put_eilvt(int offset)
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{
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return !setup_APIC_eilvt(offset, 0, 0, 1);
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}
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static inline int ibs_eilvt_valid(void)
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{
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int offset;
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u64 val;
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int valid = 0;
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preempt_disable();
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rdmsrl(MSR_AMD64_IBSCTL, val);
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offset = val & IBSCTL_LVT_OFFSET_MASK;
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if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
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pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
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smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
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goto out;
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}
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if (!get_eilvt(offset)) {
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pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
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smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
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goto out;
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}
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valid = 1;
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out:
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preempt_enable();
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return valid;
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}
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static inline int get_ibs_offset(void)
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{
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u64 val;
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rdmsrl(MSR_AMD64_IBSCTL, val);
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if (!(val & IBSCTL_LVT_OFFSET_VALID))
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return -EINVAL;
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return val & IBSCTL_LVT_OFFSET_MASK;
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}
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static void setup_APIC_ibs(void)
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{
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int offset;
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offset = get_ibs_offset();
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if (offset < 0)
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goto failed;
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if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
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return;
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failed:
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pr_warn("oprofile: IBS APIC setup failed on cpu #%d\n",
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smp_processor_id());
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}
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static void clear_APIC_ibs(void)
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{
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int offset;
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offset = get_ibs_offset();
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if (offset >= 0)
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setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
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}
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
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@ -473,15 +377,6 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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val |= op_x86_get_ctrl(model, &counter_config[virt]);
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wrmsrl(msrs->controls[i].addr, val);
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}
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if (ibs_caps)
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setup_APIC_ibs();
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}
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static void op_amd_cpu_shutdown(void)
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{
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if (ibs_caps)
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clear_APIC_ibs();
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}
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static int op_amd_check_ctrs(struct pt_regs * const regs,
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@ -544,86 +439,6 @@ static void op_amd_stop(struct op_msrs const * const msrs)
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op_amd_stop_ibs();
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}
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static int setup_ibs_ctl(int ibs_eilvt_off)
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{
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struct pci_dev *cpu_cfg;
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int nodes;
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u32 value = 0;
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nodes = 0;
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cpu_cfg = NULL;
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do {
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cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
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PCI_DEVICE_ID_AMD_10H_NB_MISC,
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cpu_cfg);
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if (!cpu_cfg)
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break;
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++nodes;
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pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
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| IBSCTL_LVT_OFFSET_VALID);
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pci_read_config_dword(cpu_cfg, IBSCTL, &value);
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if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
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pci_dev_put(cpu_cfg);
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printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
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"IBSCTL = 0x%08x\n", value);
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return -EINVAL;
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}
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} while (1);
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if (!nodes) {
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printk(KERN_DEBUG "No CPU node configured for IBS\n");
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return -ENODEV;
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}
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return 0;
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}
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/*
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* This runs only on the current cpu. We try to find an LVT offset and
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* setup the local APIC. For this we must disable preemption. On
|
||||
* success we initialize all nodes with this offset. This updates then
|
||||
* the offset in the IBS_CTL per-node msr. The per-core APIC setup of
|
||||
* the IBS interrupt vector is called from op_amd_setup_ctrs()/op_-
|
||||
* amd_cpu_shutdown() using the new offset.
|
||||
*/
|
||||
static int force_ibs_eilvt_setup(void)
|
||||
{
|
||||
int offset;
|
||||
int ret;
|
||||
|
||||
preempt_disable();
|
||||
/* find the next free available EILVT entry, skip offset 0 */
|
||||
for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
|
||||
if (get_eilvt(offset))
|
||||
break;
|
||||
}
|
||||
preempt_enable();
|
||||
|
||||
if (offset == APIC_EILVT_NR_MAX) {
|
||||
printk(KERN_DEBUG "No EILVT entry available\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
ret = setup_ibs_ctl(offset);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
if (!ibs_eilvt_valid()) {
|
||||
ret = -EFAULT;
|
||||
goto out;
|
||||
}
|
||||
|
||||
pr_err(FW_BUG "using offset %d for IBS interrupts\n", offset);
|
||||
pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");
|
||||
|
||||
return 0;
|
||||
out:
|
||||
preempt_disable();
|
||||
put_eilvt(offset);
|
||||
preempt_enable();
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* check and reserve APIC extended interrupt LVT offset for IBS if
|
||||
* available
|
||||
|
|
@ -636,17 +451,6 @@ static void init_ibs(void)
|
|||
if (!ibs_caps)
|
||||
return;
|
||||
|
||||
if (ibs_eilvt_valid())
|
||||
goto out;
|
||||
|
||||
if (!force_ibs_eilvt_setup())
|
||||
goto out;
|
||||
|
||||
/* Failed to setup ibs */
|
||||
ibs_caps = 0;
|
||||
return;
|
||||
|
||||
out:
|
||||
printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n", ibs_caps);
|
||||
}
|
||||
|
||||
|
|
@ -729,7 +533,6 @@ struct op_x86_model_spec op_amd_spec = {
|
|||
.init = op_amd_init,
|
||||
.fill_in_addresses = &op_amd_fill_in_addresses,
|
||||
.setup_ctrs = &op_amd_setup_ctrs,
|
||||
.cpu_down = &op_amd_cpu_shutdown,
|
||||
.check_ctrs = &op_amd_check_ctrs,
|
||||
.start = &op_amd_start,
|
||||
.stop = &op_amd_stop,
|
||||
|
|
|
|||
|
|
@ -43,7 +43,6 @@ struct op_x86_model_spec {
|
|||
int (*fill_in_addresses)(struct op_msrs * const msrs);
|
||||
void (*setup_ctrs)(struct op_x86_model_spec const *model,
|
||||
struct op_msrs const * const msrs);
|
||||
void (*cpu_down)(void);
|
||||
int (*check_ctrs)(struct pt_regs * const regs,
|
||||
struct op_msrs const * const msrs);
|
||||
void (*start)(struct op_msrs const * const msrs);
|
||||
|
|
|
|||
Loading…
Reference in New Issue