ARM: dts: imx51-babbage: add pinctrl settings
Add pinctrl settings for the exsiting devices in imx51-babbage.dts. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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@ -25,23 +25,31 @@
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aips@70000000 { /* aips-1 */
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spba@70000000 {
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esdhc@70004000 { /* ESDHC1 */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1_1>;
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fsl,cd-internal;
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fsl,wp-internal;
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status = "okay";
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};
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esdhc@70008000 { /* ESDHC2 */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc2_1>;
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cd-gpios = <&gpio1 6 0>;
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wp-gpios = <&gpio1 5 0>;
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status = "okay";
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};
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uart3: serial@7000c000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3_1>;
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fsl,uart-has-rtscts;
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status = "okay";
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};
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ecspi@70010000 { /* ECSPI1 */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1_1>;
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
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status = "okay";
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@ -170,22 +178,42 @@
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};
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iomuxc@73fa8000 {
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compatible = "fsl,imx51-iomuxc-babbage";
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reg = <0x73fa8000 0x4000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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hog {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
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697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
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737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
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740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
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121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
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402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
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405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
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>;
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};
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};
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};
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uart1: serial@73fbc000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_1>;
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fsl,uart-has-rtscts;
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status = "okay";
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};
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uart2: serial@73fc0000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2_1>;
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status = "okay";
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};
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};
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aips@80000000 { /* aips-2 */
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i2c@83fc4000 { /* I2C2 */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2_1>;
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status = "okay";
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sgtl5000: codec@0a {
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@ -198,10 +226,14 @@
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};
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audmux@83fd0000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux_1>;
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status = "okay";
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};
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ethernet@83fec000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec_1>;
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phy-mode = "mii";
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status = "okay";
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};
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@ -211,6 +211,122 @@
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status = "disabled";
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};
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iomuxc@73fa8000 {
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compatible = "fsl,imx51-iomuxc";
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reg = <0x73fa8000 0x4000>;
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audmux {
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pinctrl_audmux_1: audmuxgrp-1 {
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fsl,pins = <
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384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
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386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
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389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
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391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
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>;
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};
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};
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fec {
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pinctrl_fec_1: fecgrp-1 {
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fsl,pins = <
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128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
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134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
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146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
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152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
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158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
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165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
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206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
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213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
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293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
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298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
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225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
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231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
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237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
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243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
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250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
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255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
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260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
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>;
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};
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};
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ecspi1 {
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pinctrl_ecspi1_1: ecspi1grp-1 {
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fsl,pins = <
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398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
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394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
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409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
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>;
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};
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};
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esdhc1 {
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pinctrl_esdhc1_1: esdhc1grp-1 {
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fsl,pins = <
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666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
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669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
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672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
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678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
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684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
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691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
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>;
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};
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};
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esdhc2 {
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pinctrl_esdhc2_1: esdhc2grp-1 {
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fsl,pins = <
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704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
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707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
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710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
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712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
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715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
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719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
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>;
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};
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};
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i2c2 {
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pinctrl_i2c2_1: i2c2grp-1 {
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fsl,pins = <
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449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
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454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
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>;
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};
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};
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uart1 {
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pinctrl_uart1_1: uart1grp-1 {
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fsl,pins = <
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413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
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416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
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418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
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420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
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>;
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};
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};
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uart2 {
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pinctrl_uart2_1: uart2grp-1 {
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fsl,pins = <
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423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
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426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
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>;
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};
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};
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uart3 {
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pinctrl_uart3_1: uart3grp-1 {
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fsl,pins = <
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54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
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59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
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65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
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49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
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>;
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};
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};
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};
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uart1: serial@73fbc000 {
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compatible = "fsl,imx51-uart", "fsl,imx21-uart";
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reg = <0x73fbc000 0x4000>;
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