sh: SH7780 Solution Engine board support.
This adds support for the SH7780-based Solution Engine reference board. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>hifive-unleashed-5.1
Nobuhiro Iwamatsu
Paul Mundt
parent
cd6c7ea234
commit
b75762302e
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@ -99,6 +99,14 @@ config SH_7751_SOLUTION_ENGINE
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help
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Select 7751 SolutionEngine if configuring for a Hitachi SH7751
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evaluation board.
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config SH_7780_SOLUTION_ENGINE
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bool "SolutionEngine7780"
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select SOLUTION_ENGINE
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select CPU_SUBTYPE_SH7780
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help
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Select 7780 SolutionEngine if configuring for a Renesas SH7780
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evaluation board.
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config SH_7300_SOLUTION_ENGINE
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bool "SolutionEngine7300"
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@ -89,6 +89,7 @@ core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
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# Boards
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machdir-$(CONFIG_SH_SOLUTION_ENGINE) := se/770x
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machdir-$(CONFIG_SH_7751_SOLUTION_ENGINE) := se/7751
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machdir-$(CONFIG_SH_7780_SOLUTION_ENGINE) := se/7780
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machdir-$(CONFIG_SH_7300_SOLUTION_ENGINE) := se/7300
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machdir-$(CONFIG_SH_7343_SOLUTION_ENGINE) := se/7343
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machdir-$(CONFIG_SH_73180_SOLUTION_ENGINE) := se/73180
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@ -0,0 +1,10 @@
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#
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# Makefile for the HITACHI UL SolutionEngine 7780 specific parts of the kernel
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#
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# This file is subject to the terms and conditions of the GNU General Public
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# License. See the file "COPYING" in the main directory of this archive
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# for more details.
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#
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#
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obj-y := setup.o irq.o
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@ -0,0 +1,89 @@
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/*
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* linux/arch/sh/boards/se/7780/irq.c
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*
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* Copyright (C) 2006,2007 Nobuhiro Iwamatsu
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*
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* Hitachi UL SolutionEngine 7780 Support.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/se7780.h>
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#define INTC_INTMSK0 0xFFD00044
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#define INTC_INTMSKCLR0 0xFFD00064
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static void disable_se7780_irq(unsigned int irq)
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{
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struct intc2_data *p = get_irq_chip_data(irq);
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ctrl_outl(1 << p->msk_shift, INTC_INTMSK0 + p->msk_offset);
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}
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static void enable_se7780_irq(unsigned int irq)
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{
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struct intc2_data *p = get_irq_chip_data(irq);
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ctrl_outl(1 << p->msk_shift, INTC_INTMSKCLR0 + p->msk_offset);
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}
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static struct irq_chip se7780_irq_chip __read_mostly = {
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.name = "SE7780",
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.mask = disable_se7780_irq,
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.unmask = enable_se7780_irq,
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.mask_ack = disable_se7780_irq,
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};
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static struct intc2_data intc2_irq_table[] = {
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{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT1 */
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{ 4, 0, 30, 0, 30, 3 }, /* daughter board EXTINT2 */
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{ 6, 0, 29, 0, 29, 3 }, /* daughter board EXTINT3 */
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{ 8, 0, 28, 0, 28, 3 }, /* SMC 91C111 (LAN) */
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{ 10, 0, 27, 0, 27, 3 }, /* daughter board EXTINT4 */
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{ 4, 0, 30, 0, 30, 3 }, /* daughter board EXTINT5 */
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{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT6 */
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{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT7 */
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{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT8 */
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{ 0 , 0, 24, 0, 24, 3 }, /* SM501 */
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};
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/*
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* Initialize IRQ setting
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*/
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void __init init_se7780_IRQ(void)
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{
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int i ;
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/* enable all interrupt at FPGA */
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ctrl_outw(0, FPGA_INTMSK1);
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/* mask SM501 interrupt */
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ctrl_outw((ctrl_inw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
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/* enable all interrupt at FPGA */
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ctrl_outw(0, FPGA_INTMSK2);
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/* set FPGA INTSEL register */
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/* FPGA + 0x06 */
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ctrl_outw( ((IRQPIN_SM501 << IRQPOS_SM501) |
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(IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1);
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/* FPGA + 0x08 */
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ctrl_outw(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
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(IRQPIN_EXTINT3 << IRQPOS_EXTINT3) |
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(IRQPIN_EXTINT2 << IRQPOS_EXTINT2) |
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(IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2);
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/* FPGA + 0x0A */
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ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
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for (i = 0; i < ARRAY_SIZE(intc2_irq_table); i++) {
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disable_irq_nosync(intc2_irq_table[i].irq);
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set_irq_chip_and_handler_name( intc2_irq_table[i].irq, &se7780_irq_chip,
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handle_level_irq, "level");
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set_irq_chip_data( intc2_irq_table[i].irq, &intc2_irq_table[i] );
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disable_se7780_irq(intc2_irq_table[i].irq);
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}
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}
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@ -0,0 +1,122 @@
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/*
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* linux/arch/sh/boards/se/7780/setup.c
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*
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* Copyright (C) 2006,2007 Nobuhiro Iwamatsu
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*
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* Hitachi UL SolutionEngine 7780 Support.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <asm/machvec.h>
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#include <asm/se7780.h>
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#include <asm/io.h>
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/* Heartbeat */
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static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
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static struct resource heartbeat_resources[] = {
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[0] = {
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.start = PA_LED,
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.end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device heartbeat_device = {
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.name = "heartbeat",
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.id = -1,
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.dev = {
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.platform_data = heartbeat_bit_pos,
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},
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.num_resources = ARRAY_SIZE(heartbeat_resources),
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.resource = heartbeat_resources,
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};
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/* SMC91x */
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static struct resource smc91x_eth_resources[] = {
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[0] = {
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.name = "smc91x-regs" ,
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.start = PA_LAN + 0x300,
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.end = PA_LAN + 0x300 + 0x10 ,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = SMC_IRQ,
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.end = SMC_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smc91x_eth_device = {
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.name = "smc91x",
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.id = 0,
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.dev = {
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.dma_mask = NULL, /* don't use dma */
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(smc91x_eth_resources),
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.resource = smc91x_eth_resources,
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};
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static struct platform_device *se7780_devices[] __initdata = {
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&heartbeat_device,
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&smc91x_eth_device,
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};
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static int __init se7780_devices_setup(void)
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{
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return platform_add_devices(se7780_devices,
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ARRAY_SIZE(se7780_devices));
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}
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device_initcall(se7780_devices_setup);
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#define GPIO_PHCR 0xFFEA000E
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#define GPIO_PMSELR 0xFFEA0080
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#define GPIO_PECR 0xFFEA0008
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static void __init se7780_setup(char **cmdline_p)
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{
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/* "SH-Linux" on LED Display */
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ctrl_outw( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) );
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ctrl_outw( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) );
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ctrl_outw( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) );
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ctrl_outw( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) );
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ctrl_outw( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) );
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ctrl_outw( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) );
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ctrl_outw( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) );
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ctrl_outw( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) );
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printk(KERN_INFO "Hitachi UL Solutions Engine 7780SE03 support.\n");
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/*
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* PCI REQ/GNT setting
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* REQ0/GNT0 -> USB
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* REQ1/GNT1 -> PC Card
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* REQ2/GNT2 -> Serial ATA
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* REQ3/GNT3 -> PCI slot
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*/
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ctrl_outw(0x0213, FPGA_REQSEL);
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/* GPIO setting */
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ctrl_outw(0x0000, GPIO_PECR);
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ctrl_outw(ctrl_inw(GPIO_PHCR)&0xfff3, GPIO_PHCR);
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ctrl_outw(0x0c00, GPIO_PMSELR);
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/* iVDR Power ON */
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ctrl_outw(0x0001, FPGA_IVDRPW);
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}
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/*
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* The Machine Vector
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*/
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struct sh_machine_vector mv_se7780 __initmv = {
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.mv_name = "Solution Engine 7780" ,
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.mv_setup = se7780_setup ,
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.mv_nr_irqs = 111 ,
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.mv_init_irq = init_se7780_IRQ,
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};
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ALIAS_MV(se7780)
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File diff suppressed because it is too large
Load Diff
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@ -72,12 +72,27 @@ static int __init sh7780_pci_init(void)
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}
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/* Setup the INTC */
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ctrl_outl(0x00200000, INTC_ICR0); /* INTC SH-4 Mode */
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ctrl_outl(0x00078000, INTC_INT2MSKCR); /* enable PCIINTA - PCIINTD */
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ctrl_outl(0x40000000, INTC_INTMSK1); /* disable IRL4-7 Interrupt */
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ctrl_outl(0x0000fffe, INTC_INTMSK2); /* disable IRL4-7 Interrupt */
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ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */
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ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */
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if (mach_is_7780se()) {
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/* ICR0: IRL=use separately */
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ctrl_outl(0x00C00020, INTC_ICR0);
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/* ICR1: detect low level(for 2ndcut) */
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ctrl_outl(0xAAAA0000, INTC_ICR1);
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/* INTPRI: priority=3(all) */
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ctrl_outl(0x33333333, INTC_INTPRI);
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} else {
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/* INTC SH-4 Mode */
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ctrl_outl(0x00200000, INTC_ICR0);
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/* enable PCIINTA - PCIINTD */
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ctrl_outl(0x00078000, INTC_INT2MSKCR);
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/* disable IRL4-7 Interrupt */
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ctrl_outl(0x40000000, INTC_INTMSK1);
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/* disable IRL4-7 Interrupt */
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ctrl_outl(0x0000fffe, INTC_INTMSK2);
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/* enable IRL0-3 Interrupt */
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ctrl_outl(0x80000000, INTC_INTMSKCLR1);
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/* enable IRL0-3 Interrupt */
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ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
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}
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if ((ret = sh4_pci_check_direct()) != 0)
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return ret;
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@ -147,9 +162,8 @@ int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
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* DMA interrupts...
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*/
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#ifdef CONFIG_SH_HIGHLANDER
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/* Apply any last-minute PCIC fixups */
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pci_fixup_pcic();
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#endif
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/* SH7780 init done, set central function init complete */
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/* use round robin mode to stop a device starving/overruning */
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@ -66,6 +66,22 @@
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#define SH7780_PCIPMCSR_BSE 0x046
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#define SH7780_PCICDD 0x047
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#define SH7780_PCICR 0x100 /* PCI Control Register */
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#define SH7780_PCILSR 0x104 /* PCI Local Space Register0 */
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#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */
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#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */
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#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */
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#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
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#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
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#define SH7780_PCIAIR 0x11C /* Error Address Register */
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#define SH7780_PCICIR 0x120 /* Error Command/Data Register */
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#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
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#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
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#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */
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#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */
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#define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
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#define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
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#define SH7780_PCIMBR0 0x1E0
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#define SH7780_PCIMBMR0 0x1E4
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#define SH7780_PCIMBR2 0x1F0
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@ -9,6 +9,7 @@ SE SH_SOLUTION_ENGINE
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7751SE SH_7751_SOLUTION_ENGINE
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7300SE SH_7300_SOLUTION_ENGINE
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7343SE SH_7343_SOLUTION_ENGINE
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7780SE SH_7780_SOLUTION_ENGINE
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73180SE SH_73180_SOLUTION_ENGINE
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7751SYSTEMH SH_7751_SYSTEMH
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HP6XX SH_HP6XX
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@ -0,0 +1,108 @@
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#ifndef __ASM_SH_SE7780_H
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#define __ASM_SH_SE7780_H
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/*
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* linux/include/asm-sh/se7780.h
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*
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* Copyright (C) 2006,2007 Nobuhiro Iwamatsu
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*
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* Hitachi UL SolutionEngine 7780 Support.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <asm/addrspace.h>
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/* Box specific addresses. */
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#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
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#define PA_ROM 0xa0000000 /* EPROM */
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#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
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#define PA_FROM 0xa1000000 /* Flash-ROM */
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#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
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#define PA_EXT1 0xa4000000
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#define PA_EXT1_SIZE 0x04000000
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#define PA_SM501 PA_EXT1 /* Graphic IC (SM501) */
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#define PA_SM501_SIZE PA_EXT1_SIZE /* Graphic IC (SM501) */
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#define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
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#define PA_SDRAM_SIZE 0x08000000
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#define PA_EXT4 0xb0000000
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#define PA_EXT4_SIZE 0x04000000
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#define PA_EXT_FLASH PA_EXT4 /* Expansion Flash-ROM */
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#define PA_PERIPHERAL PA_AREA6_IO /* SW6-6=ON */
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#define PA_LAN (PA_PERIPHERAL + 0) /* SMC LAN91C111 */
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#define PA_LED_DISP (PA_PERIPHERAL + 0x02000000) /* 8words LED Display */
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#define DISP_CHAR_RAM (7 << 3)
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#define DISP_SEL0_ADDR (DISP_CHAR_RAM + 0)
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#define DISP_SEL1_ADDR (DISP_CHAR_RAM + 1)
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#define DISP_SEL2_ADDR (DISP_CHAR_RAM + 2)
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#define DISP_SEL3_ADDR (DISP_CHAR_RAM + 3)
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#define DISP_SEL4_ADDR (DISP_CHAR_RAM + 4)
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#define DISP_SEL5_ADDR (DISP_CHAR_RAM + 5)
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#define DISP_SEL6_ADDR (DISP_CHAR_RAM + 6)
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#define DISP_SEL7_ADDR (DISP_CHAR_RAM + 7)
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#define DISP_UDC_RAM (5 << 3)
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#define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */
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/* FPGA register address and bit */
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#define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */
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#define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */
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#define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */
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#define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */
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#define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */
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#define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */
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#define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */
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#define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */
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#define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */
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#define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */
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#define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */
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#define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */
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#define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */
|
||||
#define PA_LED FPGA_DBG_LED
|
||||
#define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */
|
||||
#define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */
|
||||
#define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */
|
||||
|
||||
/* FPGA INTSEL position */
|
||||
/* INTSEL1 */
|
||||
#define IRQPOS_SMC91CX (0 * 4)
|
||||
#define IRQPOS_SM501 (1 * 4)
|
||||
/* INTSEL2 */
|
||||
#define IRQPOS_EXTINT1 (0 * 4)
|
||||
#define IRQPOS_EXTINT2 (1 * 4)
|
||||
#define IRQPOS_EXTINT3 (2 * 4)
|
||||
#define IRQPOS_EXTINT4 (3 * 4)
|
||||
/* INTSEL3 */
|
||||
#define IRQPOS_PCCPW (0 * 4)
|
||||
|
||||
/* IDE interrupt */
|
||||
#define IRQ_IDE0 67 /* iVDR */
|
||||
|
||||
/* SMC interrupt */
|
||||
#define SMC_IRQ 8
|
||||
|
||||
/* SM501 interrupt */
|
||||
#define SM501_IRQ 0
|
||||
|
||||
/* interrupt pin */
|
||||
#define IRQPIN_EXTINT1 0 /* IRQ0 pin */
|
||||
#define IRQPIN_EXTINT2 1 /* IRQ1 pin */
|
||||
#define IRQPIN_EXTINT3 2 /* IRQ2 pin */
|
||||
#define IRQPIN_SMC91CX 3 /* IRQ3 pin */
|
||||
#define IRQPIN_EXTINT4 4 /* IRQ4 pin */
|
||||
#define IRQPIN_PCC0 5 /* IRQ5 pin */
|
||||
#define IRQPIN_PCC2 6 /* IRQ6 pin */
|
||||
#define IRQPIN_SM501 7 /* IRQ7 pin */
|
||||
#define IRQPIN_PCCPW 7 /* IRQ7 pin */
|
||||
|
||||
/* arch/sh/boards/se/7780/irq.c */
|
||||
void init_se7780_IRQ(void);
|
||||
|
||||
#define __IO_PREFIX se7780
|
||||
#include <asm/io_generic.h>
|
||||
|
||||
#endif /* __ASM_SH_SE7780_H */
|
||||
Loading…
Reference in New Issue