drm/i915: Move fp divisor calculation into ironlake_compute_dpll()
Follow what is done in i8xx_compute_dpll() and i9xx_compute_dpll() and move the lower level details of setting crtc_state->dpll_hw_state into the _compute_dpll() function. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458576016-30348-11-git-send-email-ander.conselvan.de.oliveira@intel.com
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@ -8693,10 +8693,9 @@ static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
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return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
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}
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static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state,
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u32 *fp,
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intel_clock_t *reduced_clock, u32 *fp2)
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static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state,
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intel_clock_t *reduced_clock)
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{
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struct drm_crtc *crtc = &intel_crtc->base;
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struct drm_device *dev = crtc->dev;
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@ -8705,7 +8704,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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struct drm_connector *connector;
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struct drm_connector_state *connector_state;
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struct intel_encoder *encoder;
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uint32_t dpll;
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u32 dpll, fp, fp2;
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int factor, i;
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bool is_lvds = false, is_sdvo = false;
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@ -8738,11 +8737,19 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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} else if (crtc_state->sdvo_tv_clock)
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factor = 20;
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if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
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*fp |= FP_CB_TUNE;
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fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
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if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
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*fp2 |= FP_CB_TUNE;
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if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
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fp |= FP_CB_TUNE;
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if (reduced_clock) {
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fp2 = i9xx_dpll_compute_fp(reduced_clock);
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if (reduced_clock->m < factor * reduced_clock->n)
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fp2 |= FP_CB_TUNE;
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} else {
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fp2 = fp;
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}
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dpll = 0;
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@ -8784,14 +8791,17 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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else
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dpll |= PLL_REF_INPUT_DREFCLK;
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return dpll | DPLL_VCO_ENABLE;
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dpll |= DPLL_VCO_ENABLE;
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crtc_state->dpll_hw_state.dpll = dpll;
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crtc_state->dpll_hw_state.fp0 = fp;
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crtc_state->dpll_hw_state.fp1 = fp2;
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}
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static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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intel_clock_t reduced_clock;
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u32 dpll = 0, fp = 0, fp2 = 0;
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bool has_reduced_clock = false;
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struct intel_shared_dpll *pll;
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@ -8813,19 +8823,8 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
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return -EINVAL;
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}
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fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
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if (has_reduced_clock)
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fp2 = i9xx_dpll_compute_fp(&reduced_clock);
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else
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fp2 = fp;
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dpll = ironlake_compute_dpll(crtc, crtc_state,
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&fp, &reduced_clock,
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has_reduced_clock ? &fp2 : NULL);
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crtc_state->dpll_hw_state.dpll = dpll;
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crtc_state->dpll_hw_state.fp0 = fp;
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crtc_state->dpll_hw_state.fp1 = fp2;
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ironlake_compute_dpll(crtc, crtc_state,
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has_reduced_clock ? &reduced_clock : NULL);
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pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
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if (pll == NULL) {
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