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drm/i915/bdw: Provide a gen8 version of SRM

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GEN8 now has a qword to code for 48bit addresses.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Damien Lespiau 2014-04-07 20:24:33 +01:00 committed by Daniel Vetter
parent 7ec55f46da
commit b76bfebab5
1 changed files with 1 additions and 0 deletions
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drivers/gpu/drm/i915/i915_reg.h
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@ -267,6 +267,7 @@
*/
#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
#define MI_FLUSH_DW_STORE_INDEX (1<<21)