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drm/amd/display: mclk level can't be 0. 

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hifive-unleashed-5.1
Rex Zhu 2017-02-06 12:37:44 +08:00 committed by Alex Deucher
parent ca709397b5
commit b7e2439c78
1 changed files with 4 additions and 4 deletions
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8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
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@ -357,8 +357,8 @@ bool dm_pp_get_clock_levels_by_type(
* Than means the previous one is the highest
* non-boosted one. */
DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
dc_clks->num_levels, i + 1);
dc_clks->num_levels = i;
dc_clks->num_levels, i);
dc_clks->num_levels = i > 0 ? i : 1;
break;
}
}
@ -366,8 +366,8 @@ bool dm_pp_get_clock_levels_by_type(
for (i = 0; i < dc_clks->num_levels; i++) {
if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
dc_clks->num_levels, i + 1);
dc_clks->num_levels = i;
dc_clks->num_levels, i);
dc_clks->num_levels = i > 0 ? i : 1;
break;
}
}