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clk: ingenic: jz4740: Fix gating of UDC clock 

The UDC clock is gated when the bit is cleared, not when it is set.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Fixes: 2b555a4b9c ("clk: ingenic: Add missing flag for UDC clock")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
hifive-unleashed-5.1
Paul Cercueil 2019-01-25 12:34:36 -03:00 committed by Stephen Boyd
parent bfeffd1552
commit b7e29924a1
1 changed files with 1 additions and 1 deletions
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drivers/clk/ingenic/jz4740-cgu.c
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@ -165,7 +165,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
.mux = { CGU_REG_CPCCR, 29, 1 },
.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
.gate = { CGU_REG_SCR, 6 },
.gate = { CGU_REG_SCR, 6, true },
},
/* Gate-only clocks */