MLK-23250-10: drm: imx: hdmi: Add iMX8MP hdmi driver
Add iMX8MP hdmi driver. Basci hdmi video function is working. EDID function is working. HPD basic working but not stable enough for stress test, may not work in some TVs. HDMI GP audio function added. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>5.4-rM2-2.2.x-imx-squashed
Sandor Yu
parent
54ec768dc7
commit
b82d0af62f
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@ -180,6 +180,7 @@ struct dw_hdmi {
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spinlock_t audio_lock;
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struct mutex audio_mutex;
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unsigned int sample_rate;
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unsigned int channels;
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unsigned int audio_cts;
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unsigned int audio_n;
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bool audio_enable;
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@ -542,6 +543,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
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n = 4096;
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else if (pixel_clk == 74176000 || pixel_clk == 148352000)
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n = 11648;
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else if (pixel_clk == 297000000)
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n = 3072;
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else
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n = 4096;
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n *= mult;
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@ -554,6 +557,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
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n = 17836;
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else if (pixel_clk == 148352000)
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n = 8918;
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else if (pixel_clk == 297000000)
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n = 4704;
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else
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n = 6272;
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n *= mult;
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@ -568,6 +573,8 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
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n = 11648;
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else if (pixel_clk == 148352000)
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n = 5824;
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else if (pixel_clk == 297000000)
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n = 5120;
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else
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n = 6144;
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n *= mult;
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@ -593,7 +600,7 @@ static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
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config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
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/* Only compute CTS when using internal AHB audio */
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if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
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if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) {
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/*
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* Compute the CTS value from the N value. Note that CTS and N
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* can be up to 20 bits in total, so we need 64-bit math. Also
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@ -650,6 +657,7 @@ void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
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u8 layout;
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mutex_lock(&hdmi->audio_mutex);
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hdmi->channels = cnt;
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/*
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* For >2 channel PCM audio, we need to select layout 1
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@ -690,6 +698,84 @@ static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
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hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
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}
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static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi)
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{
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int sample_freq = 0x2, org_sample_freq = 0xD;
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int ch_mask = BIT(hdmi->channels) - 1;
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switch (hdmi->sample_rate) {
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case 32000:
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sample_freq = 0x03;
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org_sample_freq = 0x0C;
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hdmi_writeb(hdmi, 0x31, HDMI_FC_AUDICONF1);
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break;
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case 44100:
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sample_freq = 0x00;
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org_sample_freq = 0x0F;
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hdmi_writeb(hdmi, 0x32, HDMI_FC_AUDICONF1);
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break;
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case 48000:
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sample_freq = 0x02;
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org_sample_freq = 0x0D;
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hdmi_writeb(hdmi, 0x33, HDMI_FC_AUDICONF1);
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break;
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case 88200:
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sample_freq = 0x08;
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org_sample_freq = 0x07;
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hdmi_writeb(hdmi, 0x34, HDMI_FC_AUDICONF1);
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break;
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case 96000:
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sample_freq = 0x0A;
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org_sample_freq = 0x05;
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hdmi_writeb(hdmi, 0x35, HDMI_FC_AUDICONF1);
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break;
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case 176400:
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sample_freq = 0x0C;
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org_sample_freq = 0x03;
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hdmi_writeb(hdmi, 0x36, HDMI_FC_AUDICONF1);
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break;
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case 192000:
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sample_freq = 0x0E;
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org_sample_freq = 0x01;
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hdmi_writeb(hdmi, 0x37, HDMI_FC_AUDICONF1);
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break;
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default:
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break;
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}
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hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
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hdmi_enable_audio_clk(hdmi, true);
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hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNL0);
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hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNL2);
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hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNL3);
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hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNL4);
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hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNL5);
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hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNL6);
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hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNL7);
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hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNL8);
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hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1);
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hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2);
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hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0);
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hdmi_modb(hdmi, 0x3, 0x3, HDMI_FC_DATAUTO3);
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if (hdmi->phy.ops->enable_audio)
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hdmi->phy.ops->enable_audio(hdmi, hdmi->phy.data, hdmi->channels);
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}
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static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi)
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{
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hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
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hdmi_modb(hdmi, 0, 0x3, HDMI_FC_DATAUTO3);
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if (hdmi->phy.ops->disable_audio)
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hdmi->phy.ops->disable_audio(hdmi, hdmi->phy.data);
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hdmi_enable_audio_clk(hdmi, false);
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}
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static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
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{
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hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
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@ -1069,6 +1155,14 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi)
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HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
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hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
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val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3);
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if (color_depth == 4)
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/* disable Auto GCP when bpp 24 */
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val &= ~0x4;
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else
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val |= 0x4;
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hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3);
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hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
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HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
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@ -1267,12 +1361,20 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
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}
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void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
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{
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/* PHY reset. The reset signal is active high on Gen1 PHYs. */
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hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
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hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
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}
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EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
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void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi)
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{
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/* PHY reset. The reset signal is active high on Gen2 PHYs. */
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hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
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hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
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}
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EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
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EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset);
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void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
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{
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@ -1425,7 +1527,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi)
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if (phy->has_svsret)
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dw_hdmi_phy_enable_svsret(hdmi, 1);
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dw_hdmi_phy_reset(hdmi);
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dw_hdmi_phy_gen2_reset(hdmi);
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hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
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@ -2615,6 +2717,7 @@ __dw_hdmi_probe(struct platform_device *pdev,
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hdmi->plat_data = plat_data;
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hdmi->dev = dev;
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hdmi->sample_rate = 48000;
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hdmi->channels = 2;
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hdmi->disabled = true;
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hdmi->rxsense = true;
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hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
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@ -2830,6 +2933,24 @@ __dw_hdmi_probe(struct platform_device *pdev,
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pdevinfo.size_data = sizeof(audio);
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pdevinfo.dma_mask = DMA_BIT_MASK(32);
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hdmi->audio = platform_device_register_full(&pdevinfo);
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} else if (config3 & HDMI_CONFIG3_GPAUD) {
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struct dw_hdmi_audio_data audio;
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audio.phys = iores->start;
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audio.base = hdmi->regs;
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audio.irq = irq;
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audio.hdmi = hdmi;
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audio.eld = hdmi->connector.eld;
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hdmi->enable_audio = dw_hdmi_gp_audio_enable;
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hdmi->disable_audio = dw_hdmi_gp_audio_disable;
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pdevinfo.name = "dw-hdmi-gp-audio";
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pdevinfo.id = PLATFORM_DEVID_NONE;
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pdevinfo.data = &audio;
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pdevinfo.size_data = sizeof(audio);
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pdevinfo.dma_mask = DMA_BIT_MASK(32);
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hdmi->audio = platform_device_register_full(&pdevinfo);
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}
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if (config0 & HDMI_CONFIG0_CEC) {
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@ -158,6 +158,17 @@
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#define HDMI_FC_SPDDEVICEINF 0x1062
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#define HDMI_FC_AUDSCONF 0x1063
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#define HDMI_FC_AUDSSTAT 0x1064
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#define HDMI_FC_AUDSV 0x1065
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#define HDMI_FC_AUDSU 0x1066
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#define HDMI_FC_AUDSCHNL0 0x1067
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#define HDMI_FC_AUDSCHNL1 0x1068
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#define HDMI_FC_AUDSCHNL2 0x1069
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#define HDMI_FC_AUDSCHNL3 0x106A
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#define HDMI_FC_AUDSCHNL4 0x106B
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#define HDMI_FC_AUDSCHNL5 0x106C
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#define HDMI_FC_AUDSCHNL6 0x106D
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#define HDMI_FC_AUDSCHNL7 0x106E
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#define HDMI_FC_AUDSCHNL8 0x106F
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#define HDMI_FC_DATACH0FILL 0x1070
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#define HDMI_FC_DATACH1FILL 0x1071
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#define HDMI_FC_DATACH2FILL 0x1072
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@ -9,7 +9,9 @@
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <video/imx-ipu-v3.h>
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@ -19,13 +21,23 @@
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#include <drm/drm_encoder.h>
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#include <drm/drm_of.h>
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#include "imx8mp-hdmi-pavi.h"
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#include "imx-drm.h"
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/* GPR reg */
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struct imx_hdmi_chip_data {
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int reg_offset;
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u32 mask_bits;
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u32 shift_bit;
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};
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struct imx_hdmi {
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struct device *dev;
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struct drm_encoder encoder;
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struct dw_hdmi *hdmi;
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struct regmap *regmap;
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const struct imx_hdmi_chip_data *chip_data;
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struct phy *phy;
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};
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static inline struct imx_hdmi *enc_to_imx_hdmi(struct drm_encoder *e)
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@ -91,7 +103,7 @@ static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
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* PREEMP config 0.00
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* TX/CK level 10
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*/
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static const struct dw_hdmi_phy_config imx_phy_config[] = {
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static const struct dw_hdmi_phy_config imx6_phy_config[] = {
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/*pixelclk symbol term vlev */
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{ 216000000, 0x800d, 0x0005, 0x01ad},
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{ ~0UL, 0x0000, 0x0000, 0x0000}
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@ -100,6 +112,7 @@ static const struct dw_hdmi_phy_config imx_phy_config[] = {
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static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
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{
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struct device_node *np = hdmi->dev->of_node;
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int ret;
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hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
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if (IS_ERR(hdmi->regmap)) {
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@ -107,6 +120,14 @@ static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
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return PTR_ERR(hdmi->regmap);
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}
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hdmi->phy = devm_phy_optional_get(hdmi->dev, "hdmi");
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if (IS_ERR(hdmi->phy)) {
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ret = PTR_ERR(hdmi->phy);
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if (ret != -EPROBE_DEFER)
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dev_err(hdmi->dev, "failed to get phy\n");
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return ret;
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}
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return 0;
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}
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@ -119,9 +140,11 @@ static void dw_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
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struct imx_hdmi *hdmi = enc_to_imx_hdmi(encoder);
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int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder);
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regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
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IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
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mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
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if (hdmi->chip_data->reg_offset < 0)
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return;
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regmap_update_bits(hdmi->regmap, hdmi->chip_data->reg_offset,
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hdmi->chip_data->mask_bits, mux << hdmi->chip_data->shift_bit);
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}
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static int dw_hdmi_imx_atomic_check(struct drm_encoder *encoder,
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@ -131,6 +154,7 @@ static int dw_hdmi_imx_atomic_check(struct drm_encoder *encoder,
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struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
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imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
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imx_crtc_state->bus_flags = DRM_BUS_FLAG_DE_HIGH;
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imx_crtc_state->di_hsync_pin = 2;
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imx_crtc_state->di_vsync_pin = 3;
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@ -173,18 +197,158 @@ imx6dl_hdmi_mode_valid(struct drm_connector *con,
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return MODE_OK;
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}
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static enum drm_mode_status
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imx8mp_hdmi_mode_valid(struct drm_connector *con,
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const struct drm_display_mode *mode)
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{
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if (mode->clock < 13500)
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return MODE_CLOCK_LOW;
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if (mode->clock > 297000)
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return MODE_CLOCK_HIGH;
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/* We don't support double-clocked and Interlaced modes */
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if (mode->flags & DRM_MODE_FLAG_DBLCLK ||
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mode->flags & DRM_MODE_FLAG_INTERLACE)
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return MODE_BAD;
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return MODE_OK;
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}
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struct imx_hdmi_chip_data imx6_chip_data = {
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.reg_offset = IOMUXC_GPR3,
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.mask_bits = IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
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.shift_bit = IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT,
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};
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static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
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.mpll_cfg = imx_mpll_cfg,
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.cur_ctr = imx_cur_ctr,
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.phy_config = imx_phy_config,
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.phy_config = imx6_phy_config,
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.mode_valid = imx6q_hdmi_mode_valid,
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.phy_data = &imx6_chip_data,
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};
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static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
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.mpll_cfg = imx_mpll_cfg,
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.cur_ctr = imx_cur_ctr,
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.phy_config = imx_phy_config,
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.phy_config = imx6_phy_config,
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.mode_valid = imx6dl_hdmi_mode_valid,
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.phy_data = &imx6_chip_data,
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};
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static int imx8mp_hdmi_phy_init(struct dw_hdmi *dw_hdmi, void *data,
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struct drm_display_mode *mode)
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{
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struct imx_hdmi *hdmi = (struct imx_hdmi *)data;
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int val;
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dev_dbg(hdmi->dev, "%s\n", __func__);
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dw_hdmi_phy_reset(dw_hdmi);
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/* enable PVI */
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imx8mp_hdmi_pvi_powerup();
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imx8mp_hdmi_pvi_enable(mode);
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/* HDMI PHY power up */
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regmap_read(hdmi->regmap, 0x200, &val);
|
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val &= ~0x8;
|
||||
regmap_write(hdmi->regmap, 0x200, val);
|
||||
|
||||
if (!hdmi->phy)
|
||||
return 0;
|
||||
|
||||
phy_power_on(hdmi->phy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void imx8mp_hdmi_phy_disable(struct dw_hdmi *dw_hdmi, void *data)
|
||||
{
|
||||
struct imx_hdmi *hdmi = (struct imx_hdmi *)data;
|
||||
int val;
|
||||
|
||||
dev_dbg(hdmi->dev, "%s\n", __func__);
|
||||
if (!hdmi->phy)
|
||||
return;
|
||||
|
||||
/* disable PVI */
|
||||
imx8mp_hdmi_pvi_disable();
|
||||
imx8mp_hdmi_pvi_powerdown();
|
||||
|
||||
/* TODO Power down HDMI PHY */
|
||||
regmap_read(hdmi->regmap, 0x200, &val);
|
||||
val |= 0x8;
|
||||
regmap_write(hdmi->regmap, 0x200, val);
|
||||
}
|
||||
|
||||
static int imx8mp_hdmimix_setup(struct imx_hdmi *hdmi)
|
||||
{
|
||||
int ret;
|
||||
|
||||
struct clk_bulk_data clocks[] = {
|
||||
{ .id = "phy_int" },
|
||||
{ .id = "prep_clk" },
|
||||
{ .id = "skp_clk" },
|
||||
{ .id = "sfr_clk" },
|
||||
{ .id = "pix_clk" },
|
||||
{ .id = "cec_clk" },
|
||||
{ .id = "apb_clk" },
|
||||
{ .id = "hpi_clk" },
|
||||
{ .id = "fdcc_ref" },
|
||||
{ .id = "pipe_clk" },
|
||||
};
|
||||
|
||||
if (NULL == imx8mp_hdmi_pavi_init()) {
|
||||
dev_err(hdmi->dev, "No pavi info found\n");
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
|
||||
ret = device_reset(hdmi->dev);
|
||||
if (ret == -EPROBE_DEFER)
|
||||
return ret;
|
||||
|
||||
ret = devm_clk_bulk_get(hdmi->dev, ARRAY_SIZE(clocks), clocks);
|
||||
if (ret < 0) {
|
||||
dev_err(hdmi->dev, "No hdmimix bulk clk got\n");
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
|
||||
return clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
|
||||
}
|
||||
|
||||
void imx8mp_hdmi_enable_audio(struct dw_hdmi *dw_hdmi, void *data, int channel)
|
||||
{
|
||||
imx8mp_hdmi_pai_powerup();
|
||||
imx8mp_hdmi_pai_enable(channel);
|
||||
}
|
||||
|
||||
void imx8mp_hdmi_disable_audio(struct dw_hdmi *dw_hdmi, void *data)
|
||||
{
|
||||
imx8mp_hdmi_pai_disable();
|
||||
imx8mp_hdmi_pai_powerdown();
|
||||
}
|
||||
|
||||
static const struct dw_hdmi_phy_ops imx8mp_hdmi_phy_ops = {
|
||||
.init = imx8mp_hdmi_phy_init,
|
||||
.disable = imx8mp_hdmi_phy_disable,
|
||||
.read_hpd = dw_hdmi_phy_read_hpd,
|
||||
.update_hpd = dw_hdmi_phy_update_hpd,
|
||||
.setup_hpd = dw_hdmi_phy_setup_hpd,
|
||||
.enable_audio = imx8mp_hdmi_enable_audio,
|
||||
.disable_audio = imx8mp_hdmi_disable_audio,
|
||||
};
|
||||
|
||||
struct imx_hdmi_chip_data imx8mp_chip_data = {
|
||||
.reg_offset = -1,
|
||||
};
|
||||
|
||||
static const struct dw_hdmi_plat_data imx8mp_hdmi_drv_data = {
|
||||
.mode_valid = imx8mp_hdmi_mode_valid,
|
||||
.phy_data = &imx8mp_chip_data,
|
||||
.phy_ops = &imx8mp_hdmi_phy_ops,
|
||||
.phy_name = "samsung_dw_hdmi_phy2",
|
||||
.phy_force_vendor = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
|
||||
|
|
@ -193,6 +357,9 @@ static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
|
|||
}, {
|
||||
.compatible = "fsl,imx6dl-hdmi",
|
||||
.data = &imx6dl_hdmi_drv_data
|
||||
}, {
|
||||
.compatible = "fsl,imx8mp-hdmi",
|
||||
.data = &imx8mp_hdmi_drv_data
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
|
@ -202,7 +369,7 @@ static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
|
|||
void *data)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
const struct dw_hdmi_plat_data *plat_data;
|
||||
struct dw_hdmi_plat_data *plat_data;
|
||||
const struct of_device_id *match;
|
||||
struct drm_device *drm = data;
|
||||
struct drm_encoder *encoder;
|
||||
|
|
@ -217,9 +384,15 @@ static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
|
|||
return -ENOMEM;
|
||||
|
||||
match = of_match_node(dw_hdmi_imx_dt_ids, pdev->dev.of_node);
|
||||
plat_data = match->data;
|
||||
plat_data = devm_kmemdup(&pdev->dev, match->data,
|
||||
sizeof(*plat_data), GFP_KERNEL);
|
||||
if (!plat_data)
|
||||
return -ENOMEM;
|
||||
|
||||
hdmi->dev = &pdev->dev;
|
||||
encoder = &hdmi->encoder;
|
||||
hdmi->chip_data = plat_data->phy_data;
|
||||
plat_data->phy_data = hdmi;
|
||||
|
||||
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
|
||||
/*
|
||||
|
|
@ -241,6 +414,12 @@ static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
|
|||
|
||||
platform_set_drvdata(pdev, hdmi);
|
||||
|
||||
if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx8mp-hdmi")) {
|
||||
ret = imx8mp_hdmimix_setup(hdmi);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -118,6 +118,8 @@ struct dw_hdmi_phy_ops {
|
|||
void (*update_hpd)(struct dw_hdmi *hdmi, void *data,
|
||||
bool force, bool disabled, bool rxsense);
|
||||
void (*setup_hpd)(struct dw_hdmi *hdmi, void *data);
|
||||
void (*enable_audio)(struct dw_hdmi *hdmi, void *data, int channel);
|
||||
void (*disable_audio)(struct dw_hdmi *hdmi, void *data);
|
||||
};
|
||||
|
||||
struct dw_hdmi_plat_data {
|
||||
|
|
@ -166,9 +168,11 @@ void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address);
|
|||
void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
|
||||
unsigned char addr);
|
||||
|
||||
void dw_hdmi_phy_reset(struct dw_hdmi *hdmi);
|
||||
|
||||
void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable);
|
||||
void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable);
|
||||
void dw_hdmi_phy_reset(struct dw_hdmi *hdmi);
|
||||
void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi);
|
||||
|
||||
enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
|
||||
void *data);
|
||||
|
|
|
|||
Loading…
Reference in New Issue