drm/radeon: add some additional 6xx/7xx/EG register init
- SMX_SAR_CTL0 needs to be programmed correctly to prevent problems with memory exports in certain cases. - VC_ENHANCE needs to be initialized on 6xx/7xx. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -1932,6 +1932,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
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WREG32(SMX_DC_CTL0, smx_dc_ctl0);
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if (rdev->family <= CHIP_SUMO2)
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WREG32(SMX_SAR_CTL0, 0x00010000);
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WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
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POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
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SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
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@ -503,6 +503,7 @@
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#define SCRATCH_UMSK 0x8540
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#define SCRATCH_ADDR 0x8544
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#define SMX_SAR_CTL0 0xA008
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#define SMX_DC_CTL0 0xA020
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#define USE_HASH_FUNCTION (1 << 0)
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#define NUMBER_OF_SETS(x) ((x) << 1)
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@ -1839,6 +1839,7 @@ void r600_gpu_init(struct radeon_device *rdev)
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WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
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NUM_CLIP_SEQ(3)));
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WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
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WREG32(VC_ENHANCE, 0);
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}
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@ -485,6 +485,7 @@
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#define TC_L2_SIZE(x) ((x)<<5)
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#define L2_DISABLE_LATE_HIT (1<<9)
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#define VC_ENHANCE 0x9714
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#define VGT_CACHE_INVALIDATION 0x88C4
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#define CACHE_INVALIDATION(x) ((x)<<0)
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@ -616,6 +616,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
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ACK_FLUSH_CTL(3) |
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SYNC_FLUSH_CTL));
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if (rdev->family != CHIP_RV770)
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WREG32(SMX_SAR_CTL0, 0x00003f3f);
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db_debug3 = RREG32(DB_DEBUG3);
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db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
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switch (rdev->family) {
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@ -792,7 +795,7 @@ static void rv770_gpu_init(struct radeon_device *rdev)
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WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
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NUM_CLIP_SEQ(3)));
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WREG32(VC_ENHANCE, 0);
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}
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void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
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@ -211,6 +211,7 @@
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#define SCRATCH_UMSK 0x8540
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#define SCRATCH_ADDR 0x8544
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#define SMX_SAR_CTL0 0xA008
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#define SMX_DC_CTL0 0xA020
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#define USE_HASH_FUNCTION (1 << 0)
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#define CACHE_DEPTH(x) ((x) << 1)
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@ -310,6 +311,8 @@
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#define TCP_CNTL 0x9610
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#define TCP_CHAN_STEER 0x9614
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#define VC_ENHANCE 0x9714
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#define VGT_CACHE_INVALIDATION 0x88C4
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#define CACHE_INVALIDATION(x) ((x)<<0)
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#define VC_ONLY 0
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