Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull more irq updates from Thomas Gleixner:
"The second part of irq related updates:
- Provide EOImode for GIC[V3] irq chips, which is a prerequisite for
direct interrupt handling in [KVM] guests"
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/GIC: Fix EOImode setting for non-DT/ACPI systems
irqchip/GIC: Don't deactivate interrupts forwarded to a guest
irqchip/GIC: Convert to EOImode == 1
irqchip/GICv3: Don't deactivate interrupts forwarded to a guest
irqchip/GICv3: Convert to EOImode == 1
hifive-unleashed-5.1
Linus Torvalds
commit
b8cb642af9
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@ -31,6 +31,7 @@
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#include <asm/cputype.h>
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#include <asm/exception.h>
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#include <asm/smp_plat.h>
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#include <asm/virt.h>
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#include "irq-gic-common.h"
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@ -50,6 +51,7 @@ struct gic_chip_data {
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};
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static struct gic_chip_data gic_data __read_mostly;
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static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
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#define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
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#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
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@ -68,6 +70,11 @@ static inline int gic_irq_in_rdist(struct irq_data *d)
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return gic_irq(d) < 32;
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}
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static inline bool forwarded_irq(struct irq_data *d)
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{
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return d->handler_data != NULL;
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}
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static inline void __iomem *gic_dist_base(struct irq_data *d)
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{
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if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
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@ -231,6 +238,21 @@ static void gic_mask_irq(struct irq_data *d)
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gic_poke_irq(d, GICD_ICENABLER);
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}
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static void gic_eoimode1_mask_irq(struct irq_data *d)
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{
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gic_mask_irq(d);
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/*
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* When masking a forwarded interrupt, make sure it is
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* deactivated as well.
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*
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* This ensures that an interrupt that is getting
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* disabled/masked will not get "stuck", because there is
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* noone to deactivate it (guest is being terminated).
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*/
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if (forwarded_irq(d))
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gic_poke_irq(d, GICD_ICACTIVER);
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}
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static void gic_unmask_irq(struct irq_data *d)
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{
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gic_poke_irq(d, GICD_ISENABLER);
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@ -296,6 +318,17 @@ static void gic_eoi_irq(struct irq_data *d)
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gic_write_eoir(gic_irq(d));
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}
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static void gic_eoimode1_eoi_irq(struct irq_data *d)
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{
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/*
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* No need to deactivate an LPI, or an interrupt that
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* is is getting forwarded to a vcpu.
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*/
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if (gic_irq(d) >= 8192 || forwarded_irq(d))
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return;
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gic_write_dir(gic_irq(d));
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}
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static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned int irq = gic_irq(d);
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@ -322,6 +355,12 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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return gic_configure_irq(irq, type, base, rwp_wait);
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}
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static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
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{
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d->handler_data = vcpu;
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return 0;
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}
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static u64 gic_mpidr_to_affinity(u64 mpidr)
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{
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u64 aff;
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@ -343,15 +382,26 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
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if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
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int err;
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if (static_key_true(&supports_deactivate))
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gic_write_eoir(irqnr);
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err = handle_domain_irq(gic_data.domain, irqnr, regs);
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if (err) {
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WARN_ONCE(true, "Unexpected interrupt received!\n");
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gic_write_eoir(irqnr);
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if (static_key_true(&supports_deactivate)) {
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if (irqnr < 8192)
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gic_write_dir(irqnr);
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} else {
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gic_write_eoir(irqnr);
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}
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}
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continue;
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}
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if (irqnr < 16) {
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gic_write_eoir(irqnr);
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if (static_key_true(&supports_deactivate))
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gic_write_dir(irqnr);
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#ifdef CONFIG_SMP
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handle_IPI(irqnr, regs);
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#else
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@ -451,8 +501,13 @@ static void gic_cpu_sys_reg_init(void)
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/* Set priority mask register */
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gic_write_pmr(DEFAULT_PMR_VALUE);
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/* EOI deactivates interrupt too (mode 0) */
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gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
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if (static_key_true(&supports_deactivate)) {
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/* EOI drops priority only (mode 1) */
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gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
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} else {
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/* EOI deactivates interrupt too (mode 0) */
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gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
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}
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/* ... and let's hit the road... */
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gic_write_grpen1(1);
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@ -661,11 +716,29 @@ static struct irq_chip gic_chip = {
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.flags = IRQCHIP_SET_TYPE_MASKED,
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};
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static struct irq_chip gic_eoimode1_chip = {
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.name = "GICv3",
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.irq_mask = gic_eoimode1_mask_irq,
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.irq_unmask = gic_unmask_irq,
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.irq_eoi = gic_eoimode1_eoi_irq,
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.irq_set_type = gic_set_type,
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.irq_set_affinity = gic_set_affinity,
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.irq_get_irqchip_state = gic_irq_get_irqchip_state,
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.irq_set_irqchip_state = gic_irq_set_irqchip_state,
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.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
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.flags = IRQCHIP_SET_TYPE_MASKED,
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};
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#define GIC_ID_NR (1U << gic_data.rdists.id_bits)
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static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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struct irq_chip *chip = &gic_chip;
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if (static_key_true(&supports_deactivate))
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chip = &gic_eoimode1_chip;
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/* SGIs are private to the core kernel */
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if (hw < 16)
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return -EPERM;
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@ -679,13 +752,13 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
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/* PPIs */
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if (hw < 32) {
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irq_set_percpu_devid(irq);
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irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
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irq_domain_set_info(d, irq, hw, chip, d->host_data,
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handle_percpu_devid_irq, NULL, NULL);
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set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
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}
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/* SPIs */
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if (hw >= 32 && hw < gic_data.irq_nr) {
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irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
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irq_domain_set_info(d, irq, hw, chip, d->host_data,
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handle_fasteoi_irq, NULL, NULL);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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@ -693,7 +766,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
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if (hw >= 8192 && hw < GIC_ID_NR) {
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if (!gic_dist_supports_lpis())
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return -EPERM;
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irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
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irq_domain_set_info(d, irq, hw, chip, d->host_data,
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handle_fasteoi_irq, NULL, NULL);
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set_irq_flags(irq, IRQF_VALID);
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}
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@ -820,6 +893,12 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
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if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
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redist_stride = 0;
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if (!is_hyp_mode_available())
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static_key_slow_dec(&supports_deactivate);
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if (static_key_true(&supports_deactivate))
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pr_info("GIC: Using split EOI/Deactivate mode\n");
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gic_data.dist_base = dist_base;
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gic_data.redist_regions = rdist_regs;
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gic_data.nr_redist_regions = nr_redist_regions;
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@ -47,6 +47,7 @@
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#include <asm/irq.h>
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#include <asm/exception.h>
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#include <asm/smp_plat.h>
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#include <asm/virt.h>
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#include "irq-gic-common.h"
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@ -82,6 +83,8 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
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#define NR_GIC_CPU_IF 8
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static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
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static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
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#ifndef MAX_GIC_NR
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#define MAX_GIC_NR 1
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#endif
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@ -137,6 +140,36 @@ static inline unsigned int gic_irq(struct irq_data *d)
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return d->hwirq;
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}
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static inline bool cascading_gic_irq(struct irq_data *d)
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{
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void *data = irq_data_get_irq_handler_data(d);
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/*
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* If handler_data pointing to one of the secondary GICs, then
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* this is a cascading interrupt, and it cannot possibly be
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* forwarded.
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*/
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if (data >= (void *)(gic_data + 1) &&
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data < (void *)(gic_data + MAX_GIC_NR))
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return true;
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return false;
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}
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static inline bool forwarded_irq(struct irq_data *d)
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{
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/*
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* A forwarded interrupt:
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* - is on the primary GIC
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* - has its handler_data set to a value
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* - that isn't a secondary GIC
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*/
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if (d->handler_data && !cascading_gic_irq(d))
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return true;
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return false;
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}
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/*
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* Routines to acknowledge, disable and enable interrupts
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*/
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@ -157,6 +190,21 @@ static void gic_mask_irq(struct irq_data *d)
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gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
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}
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static void gic_eoimode1_mask_irq(struct irq_data *d)
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{
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gic_mask_irq(d);
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/*
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* When masking a forwarded interrupt, make sure it is
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* deactivated as well.
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*
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* This ensures that an interrupt that is getting
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* disabled/masked will not get "stuck", because there is
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* noone to deactivate it (guest is being terminated).
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*/
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if (forwarded_irq(d))
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gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
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}
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static void gic_unmask_irq(struct irq_data *d)
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{
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gic_poke_irq(d, GIC_DIST_ENABLE_SET);
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@ -167,6 +215,15 @@ static void gic_eoi_irq(struct irq_data *d)
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writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
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}
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static void gic_eoimode1_eoi_irq(struct irq_data *d)
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{
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/* Do not deactivate an IRQ forwarded to a vcpu. */
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if (forwarded_irq(d))
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return;
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writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
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}
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static int gic_irq_set_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which, bool val)
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{
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@ -233,6 +290,16 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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return gic_configure_irq(gicirq, type, base, NULL);
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}
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static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
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{
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/* Only interrupts on the primary GIC can be forwarded to a vcpu. */
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if (cascading_gic_irq(d))
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return -EINVAL;
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d->handler_data = vcpu;
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return 0;
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}
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#ifdef CONFIG_SMP
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static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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bool force)
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@ -272,11 +339,15 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
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irqnr = irqstat & GICC_IAR_INT_ID_MASK;
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if (likely(irqnr > 15 && irqnr < 1021)) {
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if (static_key_true(&supports_deactivate))
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writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
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handle_domain_irq(gic->domain, irqnr, regs);
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continue;
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}
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if (irqnr < 16) {
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writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
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if (static_key_true(&supports_deactivate))
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writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
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#ifdef CONFIG_SMP
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handle_IPI(irqnr, regs);
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#endif
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@ -329,6 +400,23 @@ static struct irq_chip gic_chip = {
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IRQCHIP_MASK_ON_SUSPEND,
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};
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static struct irq_chip gic_eoimode1_chip = {
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.name = "GICv2",
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.irq_mask = gic_eoimode1_mask_irq,
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.irq_unmask = gic_unmask_irq,
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.irq_eoi = gic_eoimode1_eoi_irq,
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.irq_set_type = gic_set_type,
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#ifdef CONFIG_SMP
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.irq_set_affinity = gic_set_affinity,
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#endif
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.irq_get_irqchip_state = gic_irq_get_irqchip_state,
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.irq_set_irqchip_state = gic_irq_set_irqchip_state,
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.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
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.flags = IRQCHIP_SET_TYPE_MASKED |
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IRQCHIP_SKIP_SET_WAKE |
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IRQCHIP_MASK_ON_SUSPEND,
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};
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void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
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{
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if (gic_nr >= MAX_GIC_NR)
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|
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@ -360,6 +448,10 @@ static void gic_cpu_if_up(struct gic_chip_data *gic)
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{
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void __iomem *cpu_base = gic_data_cpu_base(gic);
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u32 bypass = 0;
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u32 mode = 0;
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|
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if (static_key_true(&supports_deactivate))
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mode = GIC_CPU_CTRL_EOImodeNS;
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/*
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* Preserve bypass disable bits to be written back later
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|
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@ -367,7 +459,7 @@ static void gic_cpu_if_up(struct gic_chip_data *gic)
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bypass = readl(cpu_base + GIC_CPU_CTRL);
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bypass &= GICC_DIS_BYPASS_MASK;
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|
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writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
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writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
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}
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|
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|
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|
|
@ -803,13 +895,20 @@ void __init gic_init_physaddr(struct device_node *node)
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static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
|
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{
|
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struct irq_chip *chip = &gic_chip;
|
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|
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if (static_key_true(&supports_deactivate)) {
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if (d->host_data == (void *)&gic_data[0])
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chip = &gic_eoimode1_chip;
|
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}
|
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|
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if (hw < 32) {
|
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irq_set_percpu_devid(irq);
|
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irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
|
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irq_domain_set_info(d, irq, hw, chip, d->host_data,
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handle_percpu_devid_irq, NULL, NULL);
|
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set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
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} else {
|
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irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
|
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irq_domain_set_info(d, irq, hw, chip, d->host_data,
|
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handle_fasteoi_irq, NULL, NULL);
|
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
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}
|
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|
|
@ -894,7 +993,7 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
|
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.xlate = gic_irq_domain_xlate,
|
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};
|
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|
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void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
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static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
|
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void __iomem *dist_base, void __iomem *cpu_base,
|
||||
u32 percpu_offset, struct device_node *node)
|
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{
|
||||
|
|
@ -995,6 +1094,8 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
|||
register_cpu_notifier(&gic_cpu_notifier);
|
||||
#endif
|
||||
set_handle_irq(gic_handle_irq);
|
||||
if (static_key_true(&supports_deactivate))
|
||||
pr_info("GIC: Using split EOI/Deactivate mode\n");
|
||||
}
|
||||
|
||||
gic_dist_init(gic);
|
||||
|
|
@ -1002,6 +1103,19 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
|||
gic_pm_init(gic);
|
||||
}
|
||||
|
||||
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
||||
void __iomem *dist_base, void __iomem *cpu_base,
|
||||
u32 percpu_offset, struct device_node *node)
|
||||
{
|
||||
/*
|
||||
* Non-DT/ACPI systems won't run a hypervisor, so let's not
|
||||
* bother with these...
|
||||
*/
|
||||
static_key_slow_dec(&supports_deactivate);
|
||||
__gic_init_bases(gic_nr, irq_start, dist_base, cpu_base,
|
||||
percpu_offset, node);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static int gic_cnt __initdata;
|
||||
|
||||
|
|
@ -1010,6 +1124,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
|
|||
{
|
||||
void __iomem *cpu_base;
|
||||
void __iomem *dist_base;
|
||||
struct resource cpu_res;
|
||||
u32 percpu_offset;
|
||||
int irq;
|
||||
|
||||
|
|
@ -1022,10 +1137,20 @@ gic_of_init(struct device_node *node, struct device_node *parent)
|
|||
cpu_base = of_iomap(node, 1);
|
||||
WARN(!cpu_base, "unable to map gic cpu registers\n");
|
||||
|
||||
of_address_to_resource(node, 1, &cpu_res);
|
||||
|
||||
/*
|
||||
* Disable split EOI/Deactivate if either HYP is not available
|
||||
* or the CPU interface is too small.
|
||||
*/
|
||||
if (gic_cnt == 0 && (!is_hyp_mode_available() ||
|
||||
resource_size(&cpu_res) < SZ_8K))
|
||||
static_key_slow_dec(&supports_deactivate);
|
||||
|
||||
if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
|
||||
percpu_offset = 0;
|
||||
|
||||
gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
|
||||
__gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
|
||||
if (!gic_cnt)
|
||||
gic_init_physaddr(node);
|
||||
|
||||
|
|
@ -1140,12 +1265,20 @@ gic_v2_acpi_init(struct acpi_table_header *table)
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable split EOI/Deactivate if HYP is not available. ACPI
|
||||
* guarantees that we'll always have a GICv2, so the CPU
|
||||
* interface will always be the right size.
|
||||
*/
|
||||
if (!is_hyp_mode_available())
|
||||
static_key_slow_dec(&supports_deactivate);
|
||||
|
||||
/*
|
||||
* Initialize zero GIC instance (no multi-GIC support). Also, set GIC
|
||||
* as default IRQ domain to allow for GSI registration and GSI to IRQ
|
||||
* number translation (see acpi_register_gsi() and acpi_gsi_to_irq()).
|
||||
*/
|
||||
gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL);
|
||||
__gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL);
|
||||
irq_set_default_host(gic_data[0].domain);
|
||||
|
||||
acpi_irq_model = ACPI_IRQ_MODEL_GIC;
|
||||
|
|
|
|||
|
|
@ -104,6 +104,8 @@
|
|||
#define GICR_SYNCR 0x00C0
|
||||
#define GICR_MOVLPIR 0x0100
|
||||
#define GICR_MOVALLR 0x0110
|
||||
#define GICR_ISACTIVER GICD_ISACTIVER
|
||||
#define GICR_ICACTIVER GICD_ICACTIVER
|
||||
#define GICR_IDREGS GICD_IDREGS
|
||||
#define GICR_PIDR2 GICD_PIDR2
|
||||
|
||||
|
|
@ -288,6 +290,7 @@
|
|||
#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
|
||||
|
||||
#define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
|
||||
#define ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
|
||||
#define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
|
||||
#define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
|
||||
#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
|
||||
|
|
@ -385,6 +388,12 @@ static inline void gic_write_eoir(u64 irq)
|
|||
isb();
|
||||
}
|
||||
|
||||
static inline void gic_write_dir(u64 irq)
|
||||
{
|
||||
asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" (irq));
|
||||
isb();
|
||||
}
|
||||
|
||||
struct irq_domain;
|
||||
int its_cpu_init(void);
|
||||
int its_init(struct device_node *node, struct rdists *rdists,
|
||||
|
|
|
|||
|
|
@ -20,9 +20,13 @@
|
|||
#define GIC_CPU_ALIAS_BINPOINT 0x1c
|
||||
#define GIC_CPU_ACTIVEPRIO 0xd0
|
||||
#define GIC_CPU_IDENT 0xfc
|
||||
#define GIC_CPU_DEACTIVATE 0x1000
|
||||
|
||||
#define GICC_ENABLE 0x1
|
||||
#define GICC_INT_PRI_THRESHOLD 0xf0
|
||||
|
||||
#define GIC_CPU_CTRL_EOImodeNS (1 << 9)
|
||||
|
||||
#define GICC_IAR_INT_ID_MASK 0x3ff
|
||||
#define GICC_INT_SPURIOUS 1023
|
||||
#define GICC_DIS_BYPASS_MASK 0x1e0
|
||||
|
|
|
|||
Loading…
Reference in New Issue