arm64: dts: Add initial device tree support for exynos7
Add initial device tree nodes for exynos7 SoC and board dts file to support espresso board based on exynos7 SoC. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Thomas Abraham <thomas.ab@samsung.com> Cc: Rob Herring <robh@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>hifive-unleashed-5.1
Naveen Krishna Ch
Kukjin Kim
parent
97bf6af1f9
commit
b9024cbc93
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@ -2,6 +2,7 @@ dts-dirs += amd
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dts-dirs += apm
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dts-dirs += arm
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dts-dirs += cavium
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dts-dirs += exynos
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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@ -0,0 +1,5 @@
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dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb
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@ -0,0 +1,39 @@
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/*
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* SAMSUNG Exynos7 Espresso board device tree source
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "exynos7.dtsi"
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/ {
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model = "Samsung Exynos7 Espresso board based on EXYNOS7";
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compatible = "samsung,exynos7-espresso", "samsung,exynos7";
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aliases {
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serial0 = &serial_2;
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};
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chosen {
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linux,stdout-path = &serial_2;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0x0 0xC0000000>;
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};
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};
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&fin_pll {
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clock-frequency = <24000000>;
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};
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&serial_2 {
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status = "okay";
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};
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@ -0,0 +1,183 @@
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/*
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* SAMSUNG EXYNOS7 SoC device tree source
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/exynos7-clk.h>
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/ {
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compatible = "samsung,exynos7";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x0>;
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enable-method = "psci";
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x1>;
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enable-method = "psci";
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x2>;
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enable-method = "psci";
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x3>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0x18000000>;
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chipid@10000000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x10000000 0x100>;
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};
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fin_pll: xxti {
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compatible = "fixed-clock";
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clock-output-names = "fin_pll";
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#clock-cells = <0>;
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};
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gic: interrupt-controller@11001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x11001000 0x1000>,
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<0x11002000 0x1000>,
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<0x11004000 0x2000>,
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<0x11006000 0x2000>;
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};
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clock_topc: clock-controller@10570000 {
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compatible = "samsung,exynos7-clock-topc";
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reg = <0x10570000 0x10000>;
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#clock-cells = <1>;
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};
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clock_top0: clock-controller@105d0000 {
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compatible = "samsung,exynos7-clock-top0";
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reg = <0x105d0000 0xb000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
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<&clock_topc DOUT_SCLK_BUS1_PLL>,
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<&clock_topc DOUT_SCLK_CC_PLL>,
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<&clock_topc DOUT_SCLK_MFC_PLL>;
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clock-names = "fin_pll", "dout_sclk_bus0_pll",
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"dout_sclk_bus1_pll", "dout_sclk_cc_pll",
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"dout_sclk_mfc_pll";
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};
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clock_peric0: clock-controller@13610000 {
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compatible = "samsung,exynos7-clock-peric0";
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reg = <0x13610000 0xd00>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
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<&clock_top0 CLK_SCLK_UART0>;
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clock-names = "fin_pll", "dout_aclk_peric0_66",
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"sclk_uart0";
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};
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clock_peric1: clock-controller@14c80000 {
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compatible = "samsung,exynos7-clock-peric1";
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reg = <0x14c80000 0xd00>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
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<&clock_top0 CLK_SCLK_UART1>,
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<&clock_top0 CLK_SCLK_UART2>,
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<&clock_top0 CLK_SCLK_UART3>;
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clock-names = "fin_pll", "dout_aclk_peric1_66",
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"sclk_uart1", "sclk_uart2", "sclk_uart3";
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};
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clock_peris: clock-controller@10040000 {
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compatible = "samsung,exynos7-clock-peris";
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reg = <0x10040000 0xd00>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
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clock-names = "fin_pll", "dout_aclk_peris_66";
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};
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serial_0: serial@13630000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x13630000 0x100>;
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interrupts = <0 440 0>;
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clocks = <&clock_peric0 PCLK_UART0>,
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<&clock_peric0 SCLK_UART0>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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serial_1: serial@14c20000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x14c20000 0x100>;
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interrupts = <0 456 0>;
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clocks = <&clock_peric1 PCLK_UART1>,
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<&clock_peric1 SCLK_UART1>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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serial_2: serial@14c30000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x14c30000 0x100>;
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interrupts = <0 457 0>;
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clocks = <&clock_peric1 PCLK_UART2>,
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<&clock_peric1 SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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serial_3: serial@14c40000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x14c40000 0x100>;
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interrupts = <0 458 0>;
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clocks = <&clock_peric1 PCLK_UART3>,
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<&clock_peric1 SCLK_UART3>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xff01>,
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<1 14 0xff01>,
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<1 11 0xff01>,
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<1 10 0xff01>;
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};
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};
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};
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