drivers: CCI: add ARM CCI PMU support
Extend the existing CCI driver to support the PMU by registering a perf backend for it. Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Nicolas Pitre <nico@linaro.org> Cc: Dave Martin <dave.martin@linaro.org> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> [will: removed broken __init annotations] Signed-off-by: Will Deacon <will.deacon@arm.com>hifive-unleashed-5.1
Punit Agrawal
Will Deacon
parent
83bc10a275
commit
b91c8f284a
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@ -18,11 +18,21 @@
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <asm/cacheflush.h>
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#include <asm/irq_regs.h>
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#include <asm/pmu.h>
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#include <asm/smp_plat.h>
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#define DRIVER_NAME "CCI-400"
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#define DRIVER_NAME_PMU DRIVER_NAME " PMU"
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#define PMU_NAME "CCI_400"
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#define CCI_PORT_CTRL 0x0
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#define CCI_CTRL_STATUS 0xc
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@ -54,6 +64,587 @@ static unsigned int nb_cci_ports;
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static void __iomem *cci_ctrl_base;
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static unsigned long cci_ctrl_phys;
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#ifdef CONFIG_HW_PERF_EVENTS
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#define CCI_PMCR 0x0100
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#define CCI_PID2 0x0fe8
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#define CCI_PMCR_CEN 0x00000001
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#define CCI_PMCR_NCNT_MASK 0x0000f800
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#define CCI_PMCR_NCNT_SHIFT 11
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#define CCI_PID2_REV_MASK 0xf0
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#define CCI_PID2_REV_SHIFT 4
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/* Port ids */
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#define CCI_PORT_S0 0
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#define CCI_PORT_S1 1
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#define CCI_PORT_S2 2
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#define CCI_PORT_S3 3
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#define CCI_PORT_S4 4
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#define CCI_PORT_M0 5
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#define CCI_PORT_M1 6
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#define CCI_PORT_M2 7
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#define CCI_REV_R0 0
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#define CCI_REV_R1 1
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#define CCI_REV_R0_P4 4
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#define CCI_REV_R1_P2 6
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#define CCI_PMU_EVT_SEL 0x000
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#define CCI_PMU_CNTR 0x004
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#define CCI_PMU_CNTR_CTRL 0x008
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#define CCI_PMU_OVRFLW 0x00c
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#define CCI_PMU_OVRFLW_FLAG 1
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#define CCI_PMU_CNTR_BASE(idx) ((idx) * SZ_4K)
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/*
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* Instead of an event id to monitor CCI cycles, a dedicated counter is
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* provided. Use 0xff to represent CCI cycles and hope that no future revisions
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* make use of this event in hardware.
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*/
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enum cci400_perf_events {
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CCI_PMU_CYCLES = 0xff
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};
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#define CCI_PMU_EVENT_MASK 0xff
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#define CCI_PMU_EVENT_SOURCE(event) ((event >> 5) & 0x7)
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#define CCI_PMU_EVENT_CODE(event) (event & 0x1f)
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#define CCI_PMU_MAX_HW_EVENTS 5 /* CCI PMU has 4 counters + 1 cycle counter */
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#define CCI_PMU_CYCLE_CNTR_IDX 0
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#define CCI_PMU_CNTR0_IDX 1
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#define CCI_PMU_CNTR_LAST(cci_pmu) (CCI_PMU_CYCLE_CNTR_IDX + cci_pmu->num_events - 1)
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/*
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* CCI PMU event id is an 8-bit value made of two parts - bits 7:5 for one of 8
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* ports and bits 4:0 are event codes. There are different event codes
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* associated with each port type.
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*
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* Additionally, the range of events associated with the port types changed
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* between Rev0 and Rev1.
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*
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* The constants below define the range of valid codes for each port type for
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* the different revisions and are used to validate the event to be monitored.
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*/
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#define CCI_REV_R0_SLAVE_PORT_MIN_EV 0x00
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#define CCI_REV_R0_SLAVE_PORT_MAX_EV 0x13
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#define CCI_REV_R0_MASTER_PORT_MIN_EV 0x14
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#define CCI_REV_R0_MASTER_PORT_MAX_EV 0x1a
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#define CCI_REV_R1_SLAVE_PORT_MIN_EV 0x00
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#define CCI_REV_R1_SLAVE_PORT_MAX_EV 0x14
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#define CCI_REV_R1_MASTER_PORT_MIN_EV 0x00
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#define CCI_REV_R1_MASTER_PORT_MAX_EV 0x11
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struct pmu_port_event_ranges {
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u8 slave_min;
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u8 slave_max;
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u8 master_min;
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u8 master_max;
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};
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static struct pmu_port_event_ranges port_event_range[] = {
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[CCI_REV_R0] = {
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.slave_min = CCI_REV_R0_SLAVE_PORT_MIN_EV,
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.slave_max = CCI_REV_R0_SLAVE_PORT_MAX_EV,
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.master_min = CCI_REV_R0_MASTER_PORT_MIN_EV,
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.master_max = CCI_REV_R0_MASTER_PORT_MAX_EV,
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},
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[CCI_REV_R1] = {
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.slave_min = CCI_REV_R1_SLAVE_PORT_MIN_EV,
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.slave_max = CCI_REV_R1_SLAVE_PORT_MAX_EV,
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.master_min = CCI_REV_R1_MASTER_PORT_MIN_EV,
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.master_max = CCI_REV_R1_MASTER_PORT_MAX_EV,
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},
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};
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struct cci_pmu_drv_data {
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void __iomem *base;
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struct arm_pmu *cci_pmu;
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int nr_irqs;
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int irqs[CCI_PMU_MAX_HW_EVENTS];
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unsigned long active_irqs;
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struct perf_event *events[CCI_PMU_MAX_HW_EVENTS];
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unsigned long used_mask[BITS_TO_LONGS(CCI_PMU_MAX_HW_EVENTS)];
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struct pmu_port_event_ranges *port_ranges;
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struct pmu_hw_events hw_events;
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};
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static struct cci_pmu_drv_data *pmu;
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static bool is_duplicate_irq(int irq, int *irqs, int nr_irqs)
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{
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int i;
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for (i = 0; i < nr_irqs; i++)
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if (irq == irqs[i])
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return true;
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return false;
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}
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static int probe_cci_revision(void)
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{
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int rev;
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rev = readl_relaxed(cci_ctrl_base + CCI_PID2) & CCI_PID2_REV_MASK;
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rev >>= CCI_PID2_REV_SHIFT;
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if (rev <= CCI_REV_R0_P4)
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return CCI_REV_R0;
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else if (rev <= CCI_REV_R1_P2)
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return CCI_REV_R1;
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return -ENOENT;
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}
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static struct pmu_port_event_ranges *port_range_by_rev(void)
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{
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int rev = probe_cci_revision();
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if (rev < 0)
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return NULL;
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return &port_event_range[rev];
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}
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static int pmu_is_valid_slave_event(u8 ev_code)
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{
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return pmu->port_ranges->slave_min <= ev_code &&
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ev_code <= pmu->port_ranges->slave_max;
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}
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static int pmu_is_valid_master_event(u8 ev_code)
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{
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return pmu->port_ranges->master_min <= ev_code &&
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ev_code <= pmu->port_ranges->master_max;
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}
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static int pmu_validate_hw_event(u8 hw_event)
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{
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u8 ev_source = CCI_PMU_EVENT_SOURCE(hw_event);
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u8 ev_code = CCI_PMU_EVENT_CODE(hw_event);
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switch (ev_source) {
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case CCI_PORT_S0:
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case CCI_PORT_S1:
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case CCI_PORT_S2:
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case CCI_PORT_S3:
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case CCI_PORT_S4:
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/* Slave Interface */
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if (pmu_is_valid_slave_event(ev_code))
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return hw_event;
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break;
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case CCI_PORT_M0:
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case CCI_PORT_M1:
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case CCI_PORT_M2:
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/* Master Interface */
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if (pmu_is_valid_master_event(ev_code))
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return hw_event;
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break;
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}
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return -ENOENT;
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}
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static int pmu_is_valid_counter(struct arm_pmu *cci_pmu, int idx)
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{
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return CCI_PMU_CYCLE_CNTR_IDX <= idx &&
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idx <= CCI_PMU_CNTR_LAST(cci_pmu);
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}
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static u32 pmu_read_register(int idx, unsigned int offset)
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{
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return readl_relaxed(pmu->base + CCI_PMU_CNTR_BASE(idx) + offset);
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}
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static void pmu_write_register(u32 value, int idx, unsigned int offset)
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{
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return writel_relaxed(value, pmu->base + CCI_PMU_CNTR_BASE(idx) + offset);
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}
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static void pmu_disable_counter(int idx)
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{
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pmu_write_register(0, idx, CCI_PMU_CNTR_CTRL);
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}
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static void pmu_enable_counter(int idx)
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{
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pmu_write_register(1, idx, CCI_PMU_CNTR_CTRL);
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}
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static void pmu_set_event(int idx, unsigned long event)
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{
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event &= CCI_PMU_EVENT_MASK;
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pmu_write_register(event, idx, CCI_PMU_EVT_SEL);
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}
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static u32 pmu_get_max_counters(void)
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{
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u32 n_cnts = (readl_relaxed(cci_ctrl_base + CCI_PMCR) &
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CCI_PMCR_NCNT_MASK) >> CCI_PMCR_NCNT_SHIFT;
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/* add 1 for cycle counter */
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return n_cnts + 1;
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}
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static struct pmu_hw_events *pmu_get_hw_events(void)
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{
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return &pmu->hw_events;
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}
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static int pmu_get_event_idx(struct pmu_hw_events *hw, struct perf_event *event)
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{
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struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hw_event = &event->hw;
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unsigned long cci_event = hw_event->config_base & CCI_PMU_EVENT_MASK;
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int idx;
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if (cci_event == CCI_PMU_CYCLES) {
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if (test_and_set_bit(CCI_PMU_CYCLE_CNTR_IDX, hw->used_mask))
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return -EAGAIN;
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return CCI_PMU_CYCLE_CNTR_IDX;
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}
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for (idx = CCI_PMU_CNTR0_IDX; idx <= CCI_PMU_CNTR_LAST(cci_pmu); ++idx)
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if (!test_and_set_bit(idx, hw->used_mask))
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return idx;
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/* No counters available */
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return -EAGAIN;
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}
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static int pmu_map_event(struct perf_event *event)
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{
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int mapping;
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u8 config = event->attr.config & CCI_PMU_EVENT_MASK;
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if (event->attr.type < PERF_TYPE_MAX)
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return -ENOENT;
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if (config == CCI_PMU_CYCLES)
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mapping = config;
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else
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mapping = pmu_validate_hw_event(config);
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return mapping;
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}
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static int pmu_request_irq(struct arm_pmu *cci_pmu, irq_handler_t handler)
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{
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int i;
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struct platform_device *pmu_device = cci_pmu->plat_device;
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if (unlikely(!pmu_device))
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return -ENODEV;
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if (pmu->nr_irqs < 1) {
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dev_err(&pmu_device->dev, "no irqs for CCI PMUs defined\n");
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return -ENODEV;
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}
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/*
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* Register all available CCI PMU interrupts. In the interrupt handler
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* we iterate over the counters checking for interrupt source (the
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* overflowing counter) and clear it.
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*
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* This should allow handling of non-unique interrupt for the counters.
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*/
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for (i = 0; i < pmu->nr_irqs; i++) {
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int err = request_irq(pmu->irqs[i], handler, IRQF_SHARED,
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"arm-cci-pmu", cci_pmu);
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if (err) {
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dev_err(&pmu_device->dev, "unable to request IRQ%d for ARM CCI PMU counters\n",
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pmu->irqs[i]);
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return err;
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}
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set_bit(i, &pmu->active_irqs);
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}
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return 0;
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}
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static irqreturn_t pmu_handle_irq(int irq_num, void *dev)
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{
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unsigned long flags;
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struct arm_pmu *cci_pmu = (struct arm_pmu *)dev;
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struct pmu_hw_events *events = cci_pmu->get_hw_events();
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struct perf_sample_data data;
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struct pt_regs *regs;
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int idx, handled = IRQ_NONE;
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raw_spin_lock_irqsave(&events->pmu_lock, flags);
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regs = get_irq_regs();
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/*
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* Iterate over counters and update the corresponding perf events.
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* This should work regardless of whether we have per-counter overflow
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* interrupt or a combined overflow interrupt.
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*/
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for (idx = CCI_PMU_CYCLE_CNTR_IDX; idx <= CCI_PMU_CNTR_LAST(cci_pmu); idx++) {
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struct perf_event *event = events->events[idx];
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struct hw_perf_event *hw_counter;
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if (!event)
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continue;
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hw_counter = &event->hw;
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/* Did this counter overflow? */
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if (!pmu_read_register(idx, CCI_PMU_OVRFLW) & CCI_PMU_OVRFLW_FLAG)
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continue;
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pmu_write_register(CCI_PMU_OVRFLW_FLAG, idx, CCI_PMU_OVRFLW);
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handled = IRQ_HANDLED;
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armpmu_event_update(event);
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perf_sample_data_init(&data, 0, hw_counter->last_period);
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if (!armpmu_event_set_period(event))
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continue;
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if (perf_event_overflow(event, &data, regs))
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cci_pmu->disable(event);
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}
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raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
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return IRQ_RETVAL(handled);
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}
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static void pmu_free_irq(struct arm_pmu *cci_pmu)
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{
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int i;
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for (i = 0; i < pmu->nr_irqs; i++) {
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if (!test_and_clear_bit(i, &pmu->active_irqs))
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continue;
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free_irq(pmu->irqs[i], cci_pmu);
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}
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}
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static void pmu_enable_event(struct perf_event *event)
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{
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unsigned long flags;
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struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
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struct pmu_hw_events *events = cci_pmu->get_hw_events();
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struct hw_perf_event *hw_counter = &event->hw;
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int idx = hw_counter->idx;
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if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {
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dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
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return;
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}
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raw_spin_lock_irqsave(&events->pmu_lock, flags);
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/* Configure the event to count, unless you are counting cycles */
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if (idx != CCI_PMU_CYCLE_CNTR_IDX)
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pmu_set_event(idx, hw_counter->config_base);
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pmu_enable_counter(idx);
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raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
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}
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static void pmu_disable_event(struct perf_event *event)
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{
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struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hw_counter = &event->hw;
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int idx = hw_counter->idx;
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if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {
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dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
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return;
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}
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pmu_disable_counter(idx);
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}
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static void pmu_start(struct arm_pmu *cci_pmu)
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{
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u32 val;
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unsigned long flags;
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struct pmu_hw_events *events = cci_pmu->get_hw_events();
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raw_spin_lock_irqsave(&events->pmu_lock, flags);
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/* Enable all the PMU counters. */
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val = readl_relaxed(cci_ctrl_base + CCI_PMCR) | CCI_PMCR_CEN;
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writel(val, cci_ctrl_base + CCI_PMCR);
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raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
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}
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static void pmu_stop(struct arm_pmu *cci_pmu)
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{
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u32 val;
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unsigned long flags;
|
||||
struct pmu_hw_events *events = cci_pmu->get_hw_events();
|
||||
|
||||
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
||||
|
||||
/* Disable all the PMU counters. */
|
||||
val = readl_relaxed(cci_ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN;
|
||||
writel(val, cci_ctrl_base + CCI_PMCR);
|
||||
|
||||
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
||||
}
|
||||
|
||||
static u32 pmu_read_counter(struct perf_event *event)
|
||||
{
|
||||
struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
|
||||
struct hw_perf_event *hw_counter = &event->hw;
|
||||
int idx = hw_counter->idx;
|
||||
u32 value;
|
||||
|
||||
if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {
|
||||
dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
|
||||
return 0;
|
||||
}
|
||||
value = pmu_read_register(idx, CCI_PMU_CNTR);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static void pmu_write_counter(struct perf_event *event, u32 value)
|
||||
{
|
||||
struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
|
||||
struct hw_perf_event *hw_counter = &event->hw;
|
||||
int idx = hw_counter->idx;
|
||||
|
||||
if (unlikely(!pmu_is_valid_counter(cci_pmu, idx)))
|
||||
dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
|
||||
else
|
||||
pmu_write_register(value, idx, CCI_PMU_CNTR);
|
||||
}
|
||||
|
||||
static int cci_pmu_init(struct arm_pmu *cci_pmu, struct platform_device *pdev)
|
||||
{
|
||||
*cci_pmu = (struct arm_pmu){
|
||||
.name = PMU_NAME,
|
||||
.max_period = (1LLU << 32) - 1,
|
||||
.get_hw_events = pmu_get_hw_events,
|
||||
.get_event_idx = pmu_get_event_idx,
|
||||
.map_event = pmu_map_event,
|
||||
.request_irq = pmu_request_irq,
|
||||
.handle_irq = pmu_handle_irq,
|
||||
.free_irq = pmu_free_irq,
|
||||
.enable = pmu_enable_event,
|
||||
.disable = pmu_disable_event,
|
||||
.start = pmu_start,
|
||||
.stop = pmu_stop,
|
||||
.read_counter = pmu_read_counter,
|
||||
.write_counter = pmu_write_counter,
|
||||
};
|
||||
|
||||
cci_pmu->plat_device = pdev;
|
||||
cci_pmu->num_events = pmu_get_max_counters();
|
||||
|
||||
return armpmu_register(cci_pmu, -1);
|
||||
}
|
||||
|
||||
static const struct of_device_id arm_cci_pmu_matches[] = {
|
||||
{
|
||||
.compatible = "arm,cci-400-pmu",
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
||||
static int cci_pmu_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
int i, ret, irq;
|
||||
|
||||
pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL);
|
||||
if (!pmu)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_warn(&pdev->dev, "Failed to get mem resource\n");
|
||||
ret = -EINVAL;
|
||||
goto memalloc_err;
|
||||
};
|
||||
|
||||
pmu->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (!pmu->base) {
|
||||
dev_warn(&pdev->dev, "Failed to ioremap\n");
|
||||
ret = -ENOMEM;
|
||||
goto memalloc_err;
|
||||
}
|
||||
|
||||
/*
|
||||
* CCI PMU has 5 overflow signals - one per counter; but some may be tied
|
||||
* together to a common interrupt.
|
||||
*/
|
||||
pmu->nr_irqs = 0;
|
||||
for (i = 0; i < CCI_PMU_MAX_HW_EVENTS; i++) {
|
||||
irq = platform_get_irq(pdev, i);
|
||||
if (irq < 0)
|
||||
break;
|
||||
|
||||
if (is_duplicate_irq(irq, pmu->irqs, pmu->nr_irqs))
|
||||
continue;
|
||||
|
||||
pmu->irqs[pmu->nr_irqs++] = irq;
|
||||
}
|
||||
|
||||
/*
|
||||
* Ensure that the device tree has as many interrupts as the number
|
||||
* of counters.
|
||||
*/
|
||||
if (i < CCI_PMU_MAX_HW_EVENTS) {
|
||||
dev_warn(&pdev->dev, "In-correct number of interrupts: %d, should be %d\n",
|
||||
i, CCI_PMU_MAX_HW_EVENTS);
|
||||
ret = -EINVAL;
|
||||
goto memalloc_err;
|
||||
}
|
||||
|
||||
pmu->port_ranges = port_range_by_rev();
|
||||
if (!pmu->port_ranges) {
|
||||
dev_warn(&pdev->dev, "CCI PMU version not supported\n");
|
||||
ret = -EINVAL;
|
||||
goto memalloc_err;
|
||||
}
|
||||
|
||||
pmu->cci_pmu = devm_kzalloc(&pdev->dev, sizeof(*(pmu->cci_pmu)), GFP_KERNEL);
|
||||
if (!pmu->cci_pmu) {
|
||||
ret = -ENOMEM;
|
||||
goto memalloc_err;
|
||||
}
|
||||
|
||||
pmu->hw_events.events = pmu->events;
|
||||
pmu->hw_events.used_mask = pmu->used_mask;
|
||||
raw_spin_lock_init(&pmu->hw_events.pmu_lock);
|
||||
|
||||
ret = cci_pmu_init(pmu->cci_pmu, pdev);
|
||||
if (ret)
|
||||
goto pmuinit_err;
|
||||
|
||||
return 0;
|
||||
|
||||
pmuinit_err:
|
||||
kfree(pmu->cci_pmu);
|
||||
memalloc_err:
|
||||
kfree(pmu);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int cci_platform_probe(struct platform_device *pdev)
|
||||
{
|
||||
if (!cci_probed())
|
||||
return -ENODEV;
|
||||
|
||||
return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HW_PERF_EVENTS */
|
||||
|
||||
struct cpu_port {
|
||||
u64 mpidr;
|
||||
u32 port;
|
||||
|
|
@ -120,7 +711,7 @@ int cci_ace_get_port(struct device_node *dn)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(cci_ace_get_port);
|
||||
|
||||
static void __init cci_ace_init_ports(void)
|
||||
static void cci_ace_init_ports(void)
|
||||
{
|
||||
int port, cpu;
|
||||
struct device_node *cpun;
|
||||
|
|
@ -386,7 +977,7 @@ static const struct of_device_id arm_cci_ctrl_if_matches[] = {
|
|||
{},
|
||||
};
|
||||
|
||||
static int __init cci_probe(void)
|
||||
static int cci_probe(void)
|
||||
{
|
||||
struct cci_nb_ports const *cci_config;
|
||||
int ret, i, nb_ace = 0, nb_ace_lite = 0;
|
||||
|
|
@ -490,7 +1081,7 @@ memalloc_err:
|
|||
static int cci_init_status = -EAGAIN;
|
||||
static DEFINE_MUTEX(cci_probing);
|
||||
|
||||
static int __init cci_init(void)
|
||||
static int cci_init(void)
|
||||
{
|
||||
if (cci_init_status != -EAGAIN)
|
||||
return cci_init_status;
|
||||
|
|
@ -502,18 +1093,55 @@ static int __init cci_init(void)
|
|||
return cci_init_status;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HW_PERF_EVENTS
|
||||
static struct platform_driver cci_pmu_driver = {
|
||||
.driver = {
|
||||
.name = DRIVER_NAME_PMU,
|
||||
.of_match_table = arm_cci_pmu_matches,
|
||||
},
|
||||
.probe = cci_pmu_probe,
|
||||
};
|
||||
|
||||
static struct platform_driver cci_platform_driver = {
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.of_match_table = arm_cci_matches,
|
||||
},
|
||||
.probe = cci_platform_probe,
|
||||
};
|
||||
|
||||
static int __init cci_platform_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = platform_driver_register(&cci_pmu_driver);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return platform_driver_register(&cci_platform_driver);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static int __init cci_platform_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
/*
|
||||
* To sort out early init calls ordering a helper function is provided to
|
||||
* check if the CCI driver has beed initialized. Function check if the driver
|
||||
* has been initialized, if not it calls the init function that probes
|
||||
* the driver and updates the return value.
|
||||
*/
|
||||
bool __init cci_probed(void)
|
||||
bool cci_probed(void)
|
||||
{
|
||||
return cci_init() == 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cci_probed);
|
||||
|
||||
early_initcall(cci_init);
|
||||
core_initcall(cci_platform_init);
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("ARM CCI support");
|
||||
|
|
|
|||
Loading…
Reference in New Issue