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clk: imx8: fix ENET RMII 50M ref clock ID 

The ENET RMII 50M SCU Ref clock was wrongly put in LPCG clock ID
definition which may overwrite the SCU clock IDs.
Fix it by move it into the correct place.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Dong Aisheng 2019-07-19 14:42:47 +08:00
parent d85732be35
commit b93157db7f
2 changed files with 4 additions and 4 deletions
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4
drivers/clk/imx/clk-imx8qxp.c
View File

@ -142,13 +142,13 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
clks[IMX_CONN_ENET0_RGMII_TXC_SEL] = imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK);
clks[IMX_CONN_ENET0_BYPASS_CLK] = imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
clks[IMX_CONN_ENET0_RGMII_RX_CLK] = imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
clks[IMX_CONN_LPCG_ENET0_RMII_REF_50MHZ_CLK] = imx_clk_scu3("enet0_ref_50_clk", NULL, IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true);
clks[IMX_CONN_ENET0_RMII_REF_50MHZ_CLK] = imx_clk_scu3("enet0_ref_50_clk", NULL, IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true);
clks[IMX_CONN_ENET1_ROOT_CLK] = imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
clks[IMX_CONN_ENET1_REF_DIV] = imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV);
clks[IMX_CONN_ENET1_RGMII_TXC_SEL] = imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK);
clks[IMX_CONN_ENET1_BYPASS_CLK] = imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
clks[IMX_CONN_ENET1_RGMII_RX_CLK] = imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
clks[IMX_CONN_LPCG_ENET1_RMII_REF_50MHZ_CLK] = imx_clk_scu3("enet1_ref_50_clk", NULL, IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true);
clks[IMX_CONN_ENET1_RMII_REF_50MHZ_CLK] = imx_clk_scu3("enet1_ref_50_clk", NULL, IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true);
clks[IMX_CONN_GPMI_BCH_IO_CLK] = imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
clks[IMX_CONN_GPMI_BCH_CLK] = imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
clks[IMX_CONN_USB2_ACLK] = imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);

4
include/dt-bindings/clock/imx8-clock.h
View File

@ -61,6 +61,8 @@
#define IMX_CONN_ENET0_RGMII_TXC_SEL 55
#define IMX_CONN_ENET1_REF_DIV 56
#define IMX_CONN_ENET1_RGMII_TXC_SEL 57
#define IMX_CONN_ENET0_RMII_REF_50MHZ_CLK 58
#define IMX_CONN_ENET1_RMII_REF_50MHZ_CLK 59
/* HSIO SS */
#define IMX_HSIO_AXI_CLK 60
@ -317,8 +319,6 @@
#define IMX_CONN_LPCG_ENET0_TXC_SAMPLING_CLK 26
#define IMX_CONN_LPCG_ENET1_TXC_SAMPLING_CLK 27
#define IMX_CONN_LPCG_ENET0_RMII_REF_50MHZ_CLK 28
#define IMX_CONN_LPCG_ENET1_RMII_REF_50MHZ_CLK 29
#define IMX_CONN_LPCG_CLK_END 30