dmaengine: imx-sdma: update sdma script for multi fifo on SAI
update sdma script for multi fifo SAI on i.mx8MQ. Besides,Add
new cell for sw_done/sw_done_selector, because PDM need enable
software done feature in sdma script(same multi fifo script).
The new fourth cell defined as below:
Bit31: sw_done
Bit15~bit0: selector
For example: 0x80000000 means sw_done enabled for done0 sector which
is for PDM on i.mx8mm.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Robin Gong
Dong Aisheng
parent
40373109c4
commit
b9416dfe21
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@ -55,7 +55,12 @@ The full ID of peripheral types can be found below.
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24 SAI
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25 HDMI Audio
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The third cell specifies the transfer priority as below.
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The third cell specifies the transfer priority and software done
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as below.
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Bit31: sw_done
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Bit15~Bit8: selector
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Bit7~Bit0: priority level
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ID transfer priority
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-------------------------
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@ -63,6 +68,9 @@ The third cell specifies the transfer priority as below.
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1 Medium
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2 Low
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For example: 0x80000000 means sw_done enabled for done0 sector and
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High priority for PDM on i.mx8mm.
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Optional properties:
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- gpr : The phandle to the General Purpose Register (GPR) node.
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@ -76,6 +76,9 @@
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#define SDMA_CHNENBL0_IMX35 0x200
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#define SDMA_CHNENBL0_IMX31 0x080
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#define SDMA_CHNPRI_0 0x100
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#define SDMA_DONE0_CONFIG 0x1000
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#define SDMA_DONE0_CONFIG_DONE_SEL 0x7
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#define SDMA_DONE0_CONFIG_DONE_DIS 0x6
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/*
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* Buffer descriptor status values.
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@ -186,6 +189,10 @@
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BIT(DMA_MEM_TO_DEV) | \
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BIT(DMA_DEV_TO_DEV))
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#define SDMA_WATERMARK_LEVEL_FIFOS_OFF 12
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#define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23)
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#define SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF 24
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/*
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* Mode/Count of data node descriptors - IPCv2
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*/
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@ -387,6 +394,9 @@ struct sdma_channel {
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bool is_ram_script;
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bool src_dualfifo;
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bool dst_dualfifo;
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unsigned int fifo_num;
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bool sw_done;
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u32 sw_done_sel;
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};
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#define IMX_DMA_SG_LOOP BIT(0)
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@ -797,6 +807,21 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
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val = readl_relaxed(sdma->regs + chnenbl);
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__set_bit(channel, &val);
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writel_relaxed(val, sdma->regs + chnenbl);
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/* Set SDMA_DONEx_CONFIG is sw_done enabled */
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if (sdmac->sw_done) {
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u32 offset = SDMA_DONE0_CONFIG + sdmac->sw_done_sel / 4;
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u32 done_sel = SDMA_DONE0_CONFIG_DONE_SEL +
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((sdmac->sw_done_sel % 4) << 3);
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u32 sw_done_dis = SDMA_DONE0_CONFIG_DONE_DIS +
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((sdmac->sw_done_sel % 4) << 3);
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val = readl_relaxed(sdma->regs + offset);
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__set_bit(done_sel, &val);
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__clear_bit(sw_done_dis, &val);
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writel_relaxed(val, sdma->regs + offset);
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}
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}
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static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
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@ -1045,6 +1070,9 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
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case IMX_DMATYPE_HDMI:
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emi_2_per = sdma->script_addrs->hdmi_dma_addr;
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break;
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case IMX_DMATYPE_MULTI_SAI:
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per_2_emi = sdma->script_addrs->sai_2_mcu_addr;
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emi_2_per = sdma->script_addrs->mcu_2_sai_addr;
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default:
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break;
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}
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@ -1251,6 +1279,26 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
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sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DD;
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}
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static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac)
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{
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sdmac->watermark_level &= ~(0xFF << SDMA_WATERMARK_LEVEL_FIFOS_OFF |
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SDMA_WATERMARK_LEVEL_SW_DONE |
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0xf << SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF);
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if (sdmac->sw_done)
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sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE |
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sdmac->sw_done_sel <<
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SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF;
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/* For fifo_num
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* bit 12-15 is the fifo number;
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* bit 16-19 is the fifo offset,
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* so here only need to shift left fifo_num 12 bit for watermake_level
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*/
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sdmac->watermark_level |= sdmac->fifo_num<<
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SDMA_WATERMARK_LEVEL_FIFOS_OFF;
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}
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static int sdma_config_channel(struct dma_chan *chan)
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{
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struct sdma_channel *sdmac = to_sdma_chan(chan);
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@ -1292,6 +1340,10 @@ static int sdma_config_channel(struct dma_chan *chan)
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sdmac->direction == DMA_MEM_TO_DEV &&
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sdmac->sdma->drvdata->ecspi_fixed)
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__set_bit(31, &sdmac->watermark_level);
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else if (sdmac->peripheral_type ==
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IMX_DMATYPE_MULTI_SAI)
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sdma_set_watermarklevel_for_sais(sdmac);
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__set_bit(sdmac->event_id0, sdmac->event_mask);
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}
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@ -1433,6 +1485,11 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan)
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sdmac->event_id1 = data->dma_request2;
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sdmac->src_dualfifo = data->src_dualfifo;
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sdmac->dst_dualfifo = data->dst_dualfifo;
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/* Get software done selector if sw_done enabled */
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if (data->done_sel & BIT(31)) {
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sdmac->sw_done = true;
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sdmac->sw_done_sel = (data->done_sel >> 8) & 0xff;
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}
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ret = clk_enable(sdmac->sdma->clk_ipg);
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if (ret)
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@ -1743,11 +1800,14 @@ static int sdma_config_write(struct dma_chan *chan,
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{
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struct sdma_channel *sdmac = to_sdma_chan(chan);
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sdmac->watermark_level = 0;
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if (direction == DMA_DEV_TO_MEM) {
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sdmac->per_address = dmaengine_cfg->src_addr;
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sdmac->watermark_level = dmaengine_cfg->src_maxburst *
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dmaengine_cfg->src_addr_width;
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sdmac->word_size = dmaengine_cfg->src_addr_width;
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sdmac->fifo_num = dmaengine_cfg->src_fifo_num;
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} else if (direction == DMA_DEV_TO_DEV) {
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sdmac->per_address2 = dmaengine_cfg->src_addr;
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sdmac->per_address = dmaengine_cfg->dst_addr;
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@ -1765,6 +1825,7 @@ static int sdma_config_write(struct dma_chan *chan,
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sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
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dmaengine_cfg->dst_addr_width;
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sdmac->word_size = dmaengine_cfg->dst_addr_width;
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sdmac->fifo_num = dmaengine_cfg->dst_fifo_num;
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}
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sdmac->direction = direction;
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return sdma_config_channel(chan);
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@ -2118,7 +2179,10 @@ static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
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data.dma_request = dma_spec->args[0];
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data.peripheral_type = dma_spec->args[1];
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data.priority = dma_spec->args[2];
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/* Get sw_done setting if sw_done enabled */
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if (dma_spec->args[2] & BIT(31))
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data.done_sel = dma_spec->args[2];
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data.priority = dma_spec->args[2] & 0xff;
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/*
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* init dma_request2 to zero, which is not used by the dts.
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* For P2P, dma_request2 is init from dma_request_channel(),
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@ -57,6 +57,7 @@ struct imx_dma_data {
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int priority;
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bool src_dualfifo;
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bool dst_dualfifo;
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int done_sel;
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};
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static inline int imx_dma_is_ipu(struct dma_chan *chan)
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