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clk: exynos4: Remove E4X12 prefix from SRC_DMC register 

This register is present on all Exynos4 SoCs and so the prefix is
misleading.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
hifive-unleashed-5.1
Tomasz Figa 2013-04-04 13:35:27 +09:00 committed by Kukjin Kim
parent 1f1f326763
commit b950622bdd
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/samsung/clk-exynos4.c
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@ -93,7 +93,7 @@
#define GATE_IP_PERIL 0xc950
#define E4210_GATE_IP_PERIR 0xc960
#define E4X12_MPLL_CON0 0x10108
#define E4X12_SRC_DMC 0x10200
#define SRC_DMC 0x10200
#define APLL_CON0 0x14100
#define E4210_MPLL_CON0 0x14108
#define SRC_CPU 0x14200
@ -389,7 +389,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p,
E4X12_SRC_DMC, 12, 1, "sclk_mpll"),
SRC_DMC, 12, 1, "sclk_mpll"),
MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
SRC_TOP0, 8, 1, "sclk_vpll"),
MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),