redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

dt-bindings: dmaengine: Add X1830 bindings. 

Add the dmaengine bindings for the X1830 Soc from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/1576591140-125668-3-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
alistair/sensors
周琰杰 (Zhou Yanjie) 2019-12-17 21:58:59 +08:00 committed by Vinod Koul
parent ed5a0ab415
commit b98900548b
2 changed files with 43 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/dma/jz4780-dma.txt
View File

@ -1,4 +1,4 @@
* Ingenic JZ4780 DMA Controller
* Ingenic XBurst DMA Controller
Required properties:
@ -8,10 +8,12 @@ Required properties:
* ingenic,jz4770-dma
* ingenic,jz4780-dma
* ingenic,x1000-dma
* ingenic,x1830-dma
- reg: Should contain the DMA channel registers location and length, followed
by the DMA controller registers location and length.
- interrupts: Should contain the interrupt specifier of the DMA controller.
- clocks: Should contain a clock specifier for the JZ4780/X1000 PDMA clock.
- clocks: Should contain a clock specifier for the JZ4780/X1000/X1830 PDMA
clock.
- #dma-cells: Must be <2>. Number of integer cells in the dmas property of
DMA clients (see below).

39
include/dt-bindings/dma/x1830-dma.h 100644
View File

@ -0,0 +1,39 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This header provides macros for X1830 DMA bindings.
*
* Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
*/
#ifndef __DT_BINDINGS_DMA_X1830_DMA_H__
#define __DT_BINDINGS_DMA_X1830_DMA_H__
/*
* Request type numbers for the X1830 DMA controller (written to the DRTn
* register for the channel).
*/
#define X1830_DMA_I2S0_TX 0x6
#define X1830_DMA_I2S0_RX 0x7
#define X1830_DMA_AUTO 0x8
#define X1830_DMA_SADC_RX 0x9
#define X1830_DMA_UART1_TX 0x12
#define X1830_DMA_UART1_RX 0x13
#define X1830_DMA_UART0_TX 0x14
#define X1830_DMA_UART0_RX 0x15
#define X1830_DMA_SSI0_TX 0x16
#define X1830_DMA_SSI0_RX 0x17
#define X1830_DMA_SSI1_TX 0x18
#define X1830_DMA_SSI1_RX 0x19
#define X1830_DMA_MSC0_TX 0x1a
#define X1830_DMA_MSC0_RX 0x1b
#define X1830_DMA_MSC1_TX 0x1c
#define X1830_DMA_MSC1_RX 0x1d
#define X1830_DMA_DMIC_RX 0x21
#define X1830_DMA_SMB0_TX 0x24
#define X1830_DMA_SMB0_RX 0x25
#define X1830_DMA_SMB1_TX 0x26
#define X1830_DMA_SMB1_RX 0x27
#define X1830_DMA_DES_TX 0x2e
#define X1830_DMA_DES_RX 0x2f
#endif /* __DT_BINDINGS_DMA_X1830_DMA_H__ */