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LF-58: sata: imx8: fix the calibration failure of phy 

The calibration of the SATA PHYX1 is derived from the PHYX2.
Add the release of the PHYX2 APB reset, and turn on the HW gated
pipe_pclks of PHYX2 to make sure that the calibration of SATA PHYX1
can be finished successfully.
Adjust the APB reset of SATA, it should be released firstly.
The EPCS configrations should be placed before the EPCS reset.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Richard Zhu 2019-11-27 12:24:48 +08:00
parent 947cc1408e
commit b99656aef5
1 changed files with 30 additions and 28 deletions
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58
drivers/ata/ahci_imx.c
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@ -94,6 +94,7 @@ enum {
IMX8QM_LPCG_PHYX2_PCLK0_MASK = (0x3 << 16),
IMX8QM_LPCG_PHYX2_PCLK1_MASK = (0x3 << 20),
IMX8QM_PHY_APB_RSTN_0 = BIT(0),
IMX8QM_PHY_APB_RSTN_1 = BIT(1),
IMX8QM_PHY_MODE_SATA = BIT(19),
IMX8QM_PHY_MODE_MASK = (0xf << 17),
IMX8QM_PHY_PIPE_RSTN_0 = BIT(24),
@ -651,6 +652,13 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv)
ret = imx8_sata_clk_enable(imxpriv);
if (ret)
return ret;
/* PHYX2 APB reset */
regmap_update_bits(imxpriv->gpr,
IMX8QM_CSR_PHYX2_OFFSET,
IMX8QM_PHY_APB_RSTN_0 | IMX8QM_PHY_APB_RSTN_1,
IMX8QM_PHY_APB_RSTN_0 | IMX8QM_PHY_APB_RSTN_1);
/* Configure PHYx2 PIPE_RSTN */
regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET +
IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val);
@ -674,20 +682,13 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv)
IMX8QM_PHY_PIPE_RSTN_1 |
IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1);
}
if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
/* The links of both PCIA and PCIEB of HSIO are down */
regmap_update_bits(imxpriv->gpr,
IMX8QM_LPCG_PHYX2_OFFSET,
IMX8QM_LPCG_PHYX2_PCLK0_MASK |
IMX8QM_LPCG_PHYX2_PCLK1_MASK,
0);
} else {
regmap_update_bits(imxpriv->gpr,
IMX8QM_LPCG_PHYX2_OFFSET,
IMX8QM_LPCG_PHYX2_PCLK0_MASK |
IMX8QM_LPCG_PHYX2_PCLK1_MASK,
BIT(17) | BIT(21));
}
regmap_update_bits(imxpriv->gpr,
IMX8QM_LPCG_PHYX2_OFFSET,
IMX8QM_LPCG_PHYX2_PCLK0_MASK |
IMX8QM_LPCG_PHYX2_PCLK1_MASK,
IMX8QM_LPCG_PHYX2_PCLK0_MASK |
IMX8QM_LPCG_PHYX2_PCLK1_MASK);
/* set PWR_RST and BT_RST of csr_pciea */
val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET;
@ -758,6 +759,21 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv)
IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0);
/* APB reset */
regmap_update_bits(imxpriv->gpr,
IMX8QM_CSR_PHYX1_OFFSET,
IMX8QM_PHY_APB_RSTN_0,
IMX8QM_PHY_APB_RSTN_0);
regmap_update_bits(imxpriv->gpr,
IMX8QM_CSR_SATA_OFFSET,
IMX8QM_SATA_CTRL_EPCS_TXDEEMP,
IMX8QM_SATA_CTRL_EPCS_TXDEEMP);
regmap_update_bits(imxpriv->gpr,
IMX8QM_CSR_SATA_OFFSET,
IMX8QM_SATA_CTRL_EPCS_TXDEEMP_SEL,
IMX8QM_SATA_CTRL_EPCS_TXDEEMP_SEL);
/* clear PHY RST, then set it */
regmap_update_bits(imxpriv->gpr,
IMX8QM_CSR_SATA_OFFSET,
@ -768,14 +784,6 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv)
IMX8QM_CSR_SATA_OFFSET,
IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
IMX8QM_SATA_CTRL_EPCS_PHYRESET_N);
regmap_update_bits(imxpriv->gpr,
IMX8QM_CSR_SATA_OFFSET,
IMX8QM_SATA_CTRL_EPCS_TXDEEMP,
IMX8QM_SATA_CTRL_EPCS_TXDEEMP);
regmap_update_bits(imxpriv->gpr,
IMX8QM_CSR_SATA_OFFSET,
IMX8QM_SATA_CTRL_EPCS_TXDEEMP_SEL,
IMX8QM_SATA_CTRL_EPCS_TXDEEMP_SEL);
/* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
regmap_update_bits(imxpriv->gpr,
@ -792,12 +800,6 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv)
IMX8QM_SATA_CTRL_RESET_N,
IMX8QM_SATA_CTRL_RESET_N);
/* APB reset */
regmap_update_bits(imxpriv->gpr,
IMX8QM_CSR_PHYX1_OFFSET,
IMX8QM_PHY_APB_RSTN_0,
IMX8QM_PHY_APB_RSTN_0);
for (i = 0; i < 100; i++) {
reg = IMX8QM_CSR_PHYX1_OFFSET +
IMX8QM_CSR_PHYX_STTS0_OFFSET;