drm/radeon: add register headers for CP DMA on r6xx-SI
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1035,6 +1035,53 @@
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#define PACKET3_WAIT_REG_MEM 0x3C
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#define PACKET3_WAIT_REG_MEM 0x3C
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#define PACKET3_MEM_WRITE 0x3D
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#define PACKET3_MEM_WRITE 0x3D
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#define PACKET3_INDIRECT_BUFFER 0x32
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#define PACKET3_INDIRECT_BUFFER 0x32
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#define PACKET3_CP_DMA 0x41
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/* 1. header
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* 2. SRC_ADDR_LO or DATA [31:0]
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* 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
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* SRC_ADDR_HI [7:0]
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* 4. DST_ADDR_LO [31:0]
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* 5. DST_ADDR_HI [7:0]
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* 6. COMMAND [29:22] | BYTE_COUNT [20:0]
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*/
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# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
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/* 0 - SRC_ADDR
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* 1 - GDS
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*/
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# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
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/* 0 - ME
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* 1 - PFP
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*/
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# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
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/* 0 - SRC_ADDR
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* 1 - GDS
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* 2 - DATA
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*/
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# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
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/* COMMAND */
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# define PACKET3_CP_DMA_DIS_WC (1 << 21)
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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* 3 - 8 in 64
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*/
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# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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* 3 - 8 in 64
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*/
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# define PACKET3_CP_DMA_CMD_SAS (1 << 26)
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/* 0 - memory
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* 1 - register
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*/
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# define PACKET3_CP_DMA_CMD_DAS (1 << 27)
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/* 0 - memory
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* 1 - register
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*/
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# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
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# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
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#define PACKET3_SURFACE_SYNC 0x43
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#define PACKET3_SURFACE_SYNC 0x43
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# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
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# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
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# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
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# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
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@ -1186,6 +1186,38 @@
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#define PACKET3_WAIT_REG_MEM 0x3C
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#define PACKET3_WAIT_REG_MEM 0x3C
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#define PACKET3_MEM_WRITE 0x3D
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#define PACKET3_MEM_WRITE 0x3D
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#define PACKET3_INDIRECT_BUFFER 0x32
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#define PACKET3_INDIRECT_BUFFER 0x32
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#define PACKET3_CP_DMA 0x41
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/* 1. header
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* 2. SRC_ADDR_LO [31:0]
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* 3. CP_SYNC [31] | SRC_ADDR_HI [7:0]
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* 4. DST_ADDR_LO [31:0]
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* 5. DST_ADDR_HI [7:0]
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* 6. COMMAND [29:22] | BYTE_COUNT [20:0]
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*/
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# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
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/* COMMAND */
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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* 3 - 8 in 64
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*/
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# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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* 3 - 8 in 64
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*/
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# define PACKET3_CP_DMA_CMD_SAS (1 << 26)
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/* 0 - memory
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* 1 - register
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*/
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# define PACKET3_CP_DMA_CMD_DAS (1 << 27)
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/* 0 - memory
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* 1 - register
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*/
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# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
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# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
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#define PACKET3_SURFACE_SYNC 0x43
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#define PACKET3_SURFACE_SYNC 0x43
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# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
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# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
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# define PACKET3_TC_ACTION_ENA (1 << 23)
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# define PACKET3_TC_ACTION_ENA (1 << 23)
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@ -849,6 +849,54 @@
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#define PACKET3_WAIT_REG_MEM 0x3C
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#define PACKET3_WAIT_REG_MEM 0x3C
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#define PACKET3_MEM_WRITE 0x3D
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#define PACKET3_MEM_WRITE 0x3D
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#define PACKET3_COPY_DATA 0x40
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#define PACKET3_COPY_DATA 0x40
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#define PACKET3_CP_DMA 0x41
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/* 1. header
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* 2. SRC_ADDR_LO or DATA [31:0]
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* 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
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* SRC_ADDR_HI [7:0]
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* 4. DST_ADDR_LO [31:0]
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* 5. DST_ADDR_HI [7:0]
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* 6. COMMAND [30:21] | BYTE_COUNT [20:0]
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*/
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# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
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/* 0 - SRC_ADDR
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* 1 - GDS
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*/
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# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
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/* 0 - ME
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* 1 - PFP
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*/
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# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
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/* 0 - SRC_ADDR
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* 1 - GDS
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* 2 - DATA
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*/
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# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
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/* COMMAND */
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# define PACKET3_CP_DMA_DIS_WC (1 << 21)
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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* 3 - 8 in 64
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*/
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# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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* 3 - 8 in 64
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*/
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# define PACKET3_CP_DMA_CMD_SAS (1 << 26)
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/* 0 - memory
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* 1 - register
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*/
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# define PACKET3_CP_DMA_CMD_DAS (1 << 27)
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/* 0 - memory
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* 1 - register
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*/
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# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
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# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
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# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
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#define PACKET3_PFP_SYNC_ME 0x42
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#define PACKET3_PFP_SYNC_ME 0x42
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#define PACKET3_SURFACE_SYNC 0x43
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#define PACKET3_SURFACE_SYNC 0x43
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# define PACKET3_DEST_BASE_0_ENA (1 << 0)
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# define PACKET3_DEST_BASE_0_ENA (1 << 0)
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