ARM: 7450/1: dcache: select DCACHE_WORD_ACCESS for little-endian ARMv6+ CPUs
DCACHE_WORD_ACCESS uses the word-at-a-time API for optimised string comparisons in the vfs layer. This patch implements support for load_unaligned_zeropad for ARM CPUs with native support for unaligned memory accesses (v6+) when running little-endian. Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -48,6 +48,7 @@ config ARM
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select GENERIC_CLOCKEVENTS_BROADCAST if SMP
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select GENERIC_STRNCPY_FROM_USER
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select GENERIC_STRNLEN_USER
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select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
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help
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The ARM series is a line of low-power-consumption RISC chip designs
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licensed by ARM Ltd and targeted at embedded applications and
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@ -48,6 +48,47 @@ static inline unsigned long find_zero(unsigned long mask)
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return ret;
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}
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#ifdef CONFIG_DCACHE_WORD_ACCESS
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#define zero_bytemask(mask) (mask)
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/*
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* Load an unaligned word from kernel space.
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*
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* In the (very unlikely) case of the word being a page-crosser
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* and the next page not being mapped, take the exception and
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* return zeroes in the non-existing part.
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*/
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static inline unsigned long load_unaligned_zeropad(const void *addr)
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{
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unsigned long ret, offset;
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/* Load word from unaligned pointer addr */
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asm(
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"1: ldr %0, [%2]\n"
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"2:\n"
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" .pushsection .fixup,\"ax\"\n"
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" .align 2\n"
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"3: and %1, %2, #0x3\n"
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" bic %2, %2, #0x3\n"
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" ldr %0, [%2]\n"
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" lsl %1, %1, #0x3\n"
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" lsr %0, %0, %1\n"
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" b 2b\n"
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" .popsection\n"
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" .pushsection __ex_table,\"a\"\n"
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" .align 3\n"
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" .long 1b, 3b\n"
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" .popsection"
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: "=&r" (ret), "=&r" (offset)
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: "r" (addr), "Qo" (*(unsigned long *)addr));
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return ret;
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}
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#endif /* DCACHE_WORD_ACCESS */
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#else /* __ARMEB__ */
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#include <asm-generic/word-at-a-time.h>
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#endif
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