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net: phy: broadcom: add 1000Base-X support for BCM54616S 

The BCM54616S PHY cannot work properly in RGMII->1000Base-X mode, mainly
because genphy functions are designed for copper links, and 1000Base-X
(clause 37) auto negotiation needs to be handled differently.

This patch enables 1000Base-X support for BCM54616S by customizing 3
driver callbacks, and it's verified to be working on Facebook CMM BMC
platform (RGMII->1000Base-KX):

  - probe: probe callback detects PHY's operation mode based on
    INTERF_SEL[1:0] pins and 1000X/100FX selection bit in SerDES 100-FX
    Control register.

  - config_aneg: calls genphy_c37_config_aneg when the PHY is running in
    1000Base-X mode; otherwise, genphy_config_aneg will be called.

  - read_status: calls genphy_c37_read_status when the PHY is running in
    1000Base-X mode; otherwise, genphy_read_status will be called.

Note: BCM54616S PHY can also be configured in RGMII->100Base-FX mode, and
100Base-FX support is not available as of now.

Signed-off-by: Tao Ren <taoren@fb.com>
Acked-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
alistair/sunxi64-5.5-dsi
Tao Ren 2019-10-22 11:31:08 -07:00 committed by David S. Miller
parent fa6e98cee5
commit b9bcb95315
2 changed files with 61 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

57
drivers/net/phy/broadcom.c
View File

@ -359,9 +359,9 @@ static int bcm5482_config_init(struct phy_device *phydev)
/*
* Select 1000BASE-X register set (primary SerDes)
*/
reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_MODE);
bcm_phy_write_shadow(phydev, BCM5482_SHD_MODE,
reg | BCM5482_SHD_MODE_1000BX);
reg = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE,
reg | BCM54XX_SHD_MODE_1000BX);
/*
* LED1=ACTIVITYLED, LED3=LINKSPD[2]
@ -427,12 +427,47 @@ static int bcm5481_config_aneg(struct phy_device *phydev)
return ret;
}
static int bcm54616s_probe(struct phy_device *phydev)
{
int val, intf_sel;
val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
if (val < 0)
return val;
/* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0]
* is 01b, and the link between PHY and its link partner can be
* either 1000Base-X or 100Base-FX.
* RGMII-1000Base-X is properly supported, but RGMII-100Base-FX
* support is still missing as of now.
*/
intf_sel = (val & BCM54XX_SHD_INTF_SEL_MASK) >> 1;
if (intf_sel == 1) {
val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
if (val < 0)
return val;
/* Bit 0 of the SerDes 100-FX Control register, when set
* to 1, sets the MII/RGMII -> 100BASE-FX configuration.
* When this bit is set to 0, it sets the GMII/RGMII ->
* 1000BASE-X configuration.
*/
if (!(val & BCM54616S_100FX_MODE))
phydev->dev_flags |= PHY_BCM_FLAGS_MODE_1000BX;
}
return 0;
}
static int bcm54616s_config_aneg(struct phy_device *phydev)
{
int ret;
/* Aneg firsly. */
ret = genphy_config_aneg(phydev);
if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
ret = genphy_c37_config_aneg(phydev);
else
ret = genphy_config_aneg(phydev);
/* Then we can set up the delay. */
bcm54xx_config_clock_delay(phydev);
@ -440,6 +475,18 @@ static int bcm54616s_config_aneg(struct phy_device *phydev)
return ret;
}
static int bcm54616s_read_status(struct phy_device *phydev)
{
int err;
if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
err = genphy_c37_read_status(phydev);
else
err = genphy_read_status(phydev);
return err;
}
static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
{
int val;
@ -631,6 +678,8 @@ static struct phy_driver broadcom_drivers[] = {
.config_aneg = bcm54616s_config_aneg,
.ack_interrupt = bcm_phy_ack_intr,
.config_intr = bcm_phy_config_intr,
.read_status = bcm54616s_read_status,
.probe = bcm54616s_probe,
}, {
.phy_id = PHY_ID_BCM5464,
.phy_id_mask = 0xfffffff0,

10
include/linux/brcmphy.h
View File

@ -200,9 +200,15 @@
#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
#define BCM5482_SHD_MODE 0x1f /* 11111: Mode Control Register */
#define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */
/* 10011: SerDes 100-FX Control Register */
#define BCM54616S_SHD_100FX_CTRL 0x13
#define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */
/* 11111: Mode Control Register */
#define BCM54XX_SHD_MODE 0x1f
#define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */
#define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */
/*
* EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)