lib/raid6: Add AVX2 optimized xor_syndrome functions
Implement the AVX2 optimization of RAID6 xor_syndrome functions which is simply based on sse2.c written by hpa. Cc: H. Peter Anvin <hpa@linux.intel.com> Cc: Yuanhan Liu <yuanhan.liu@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Signed-off-by: Shaohua Li <shli@fb.com>hifive-unleashed-5.1
Gayatri Kammela
Shaohua Li
parent
b58ec8b582
commit
b9bf33a8bd
232
lib/raid6/avx2.c
232
lib/raid6/avx2.c
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@ -87,9 +87,57 @@ static void raid6_avx21_gen_syndrome(int disks, size_t bytes, void **ptrs)
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kernel_fpu_end();
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}
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static void raid6_avx21_xor_syndrome(int disks, int start, int stop,
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size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = stop; /* P/Q right side optimization */
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p = dptr[disks-2]; /* XOR parity */
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q = dptr[disks-1]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
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for (d = 0 ; d < bytes ; d += 32) {
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asm volatile("vmovdqa %0,%%ymm4" :: "m" (dptr[z0][d]));
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asm volatile("vmovdqa %0,%%ymm2" : : "m" (p[d]));
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asm volatile("vpxor %ymm4,%ymm2,%ymm2");
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/* P/Q data pages */
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for (z = z0-1 ; z >= start ; z--) {
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asm volatile("vpxor %ymm5,%ymm5,%ymm5");
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asm volatile("vpcmpgtb %ymm4,%ymm5,%ymm5");
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asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
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asm volatile("vpand %ymm0,%ymm5,%ymm5");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vmovdqa %0,%%ymm5" :: "m" (dptr[z][d]));
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asm volatile("vpxor %ymm5,%ymm2,%ymm2");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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}
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/* P/Q left side optimization */
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for (z = start-1 ; z >= 0 ; z--) {
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asm volatile("vpxor %ymm5,%ymm5,%ymm5");
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asm volatile("vpcmpgtb %ymm4,%ymm5,%ymm5");
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asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
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asm volatile("vpand %ymm0,%ymm5,%ymm5");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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}
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asm volatile("vpxor %0,%%ymm4,%%ymm4" : : "m" (q[d]));
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/* Don't use movntdq for r/w memory area < cache line */
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asm volatile("vmovdqa %%ymm4,%0" : "=m" (q[d]));
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asm volatile("vmovdqa %%ymm2,%0" : "=m" (p[d]));
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_avx2x1 = {
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raid6_avx21_gen_syndrome,
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NULL, /* XOR not yet implemented */
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raid6_avx21_xor_syndrome,
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raid6_have_avx2,
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"avx2x1",
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1 /* Has cache hints */
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@ -149,9 +197,77 @@ static void raid6_avx22_gen_syndrome(int disks, size_t bytes, void **ptrs)
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kernel_fpu_end();
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}
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static void raid6_avx22_xor_syndrome(int disks, int start, int stop,
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size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = stop; /* P/Q right side optimization */
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p = dptr[disks-2]; /* XOR parity */
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q = dptr[disks-1]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
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for (d = 0 ; d < bytes ; d += 64) {
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asm volatile("vmovdqa %0,%%ymm4" :: "m" (dptr[z0][d]));
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asm volatile("vmovdqa %0,%%ymm6" :: "m" (dptr[z0][d+32]));
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asm volatile("vmovdqa %0,%%ymm2" : : "m" (p[d]));
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asm volatile("vmovdqa %0,%%ymm3" : : "m" (p[d+32]));
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asm volatile("vpxor %ymm4,%ymm2,%ymm2");
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asm volatile("vpxor %ymm6,%ymm3,%ymm3");
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/* P/Q data pages */
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for (z = z0-1 ; z >= start ; z--) {
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asm volatile("vpxor %ymm5,%ymm5,%ymm5");
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asm volatile("vpxor %ymm7,%ymm7,%ymm7");
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asm volatile("vpcmpgtb %ymm4,%ymm5,%ymm5");
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asm volatile("vpcmpgtb %ymm6,%ymm7,%ymm7");
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asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
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asm volatile("vpaddb %ymm6,%ymm6,%ymm6");
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asm volatile("vpand %ymm0,%ymm5,%ymm5");
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asm volatile("vpand %ymm0,%ymm7,%ymm7");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm7,%ymm6,%ymm6");
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asm volatile("vmovdqa %0,%%ymm5" :: "m" (dptr[z][d]));
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asm volatile("vmovdqa %0,%%ymm7"
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:: "m" (dptr[z][d+32]));
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asm volatile("vpxor %ymm5,%ymm2,%ymm2");
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asm volatile("vpxor %ymm7,%ymm3,%ymm3");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm7,%ymm6,%ymm6");
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}
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/* P/Q left side optimization */
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for (z = start-1 ; z >= 0 ; z--) {
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asm volatile("vpxor %ymm5,%ymm5,%ymm5");
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asm volatile("vpxor %ymm7,%ymm7,%ymm7");
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asm volatile("vpcmpgtb %ymm4,%ymm5,%ymm5");
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asm volatile("vpcmpgtb %ymm6,%ymm7,%ymm7");
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asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
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asm volatile("vpaddb %ymm6,%ymm6,%ymm6");
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asm volatile("vpand %ymm0,%ymm5,%ymm5");
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asm volatile("vpand %ymm0,%ymm7,%ymm7");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm7,%ymm6,%ymm6");
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}
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asm volatile("vpxor %0,%%ymm4,%%ymm4" : : "m" (q[d]));
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asm volatile("vpxor %0,%%ymm6,%%ymm6" : : "m" (q[d+32]));
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/* Don't use movntdq for r/w memory area < cache line */
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asm volatile("vmovdqa %%ymm4,%0" : "=m" (q[d]));
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asm volatile("vmovdqa %%ymm6,%0" : "=m" (q[d+32]));
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asm volatile("vmovdqa %%ymm2,%0" : "=m" (p[d]));
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asm volatile("vmovdqa %%ymm3,%0" : "=m" (p[d+32]));
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_avx2x2 = {
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raid6_avx22_gen_syndrome,
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NULL, /* XOR not yet implemented */
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raid6_avx22_xor_syndrome,
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raid6_have_avx2,
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"avx2x2",
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1 /* Has cache hints */
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@ -242,9 +358,119 @@ static void raid6_avx24_gen_syndrome(int disks, size_t bytes, void **ptrs)
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kernel_fpu_end();
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}
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static void raid6_avx24_xor_syndrome(int disks, int start, int stop,
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size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = stop; /* P/Q right side optimization */
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p = dptr[disks-2]; /* XOR parity */
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q = dptr[disks-1]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("vmovdqa %0,%%ymm0" :: "m" (raid6_avx2_constants.x1d[0]));
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for (d = 0 ; d < bytes ; d += 128) {
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asm volatile("vmovdqa %0,%%ymm4" :: "m" (dptr[z0][d]));
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asm volatile("vmovdqa %0,%%ymm6" :: "m" (dptr[z0][d+32]));
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asm volatile("vmovdqa %0,%%ymm12" :: "m" (dptr[z0][d+64]));
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asm volatile("vmovdqa %0,%%ymm14" :: "m" (dptr[z0][d+96]));
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asm volatile("vmovdqa %0,%%ymm2" : : "m" (p[d]));
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asm volatile("vmovdqa %0,%%ymm3" : : "m" (p[d+32]));
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asm volatile("vmovdqa %0,%%ymm10" : : "m" (p[d+64]));
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asm volatile("vmovdqa %0,%%ymm11" : : "m" (p[d+96]));
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asm volatile("vpxor %ymm4,%ymm2,%ymm2");
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asm volatile("vpxor %ymm6,%ymm3,%ymm3");
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asm volatile("vpxor %ymm12,%ymm10,%ymm10");
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asm volatile("vpxor %ymm14,%ymm11,%ymm11");
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/* P/Q data pages */
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for (z = z0-1 ; z >= start ; z--) {
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asm volatile("prefetchnta %0" :: "m" (dptr[z][d]));
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asm volatile("prefetchnta %0" :: "m" (dptr[z][d+64]));
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asm volatile("vpxor %ymm5,%ymm5,%ymm5");
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asm volatile("vpxor %ymm7,%ymm7,%ymm7");
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asm volatile("vpxor %ymm13,%ymm13,%ymm13");
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asm volatile("vpxor %ymm15,%ymm15,%ymm15");
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asm volatile("vpcmpgtb %ymm4,%ymm5,%ymm5");
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asm volatile("vpcmpgtb %ymm6,%ymm7,%ymm7");
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asm volatile("vpcmpgtb %ymm12,%ymm13,%ymm13");
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asm volatile("vpcmpgtb %ymm14,%ymm15,%ymm15");
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asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
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asm volatile("vpaddb %ymm6,%ymm6,%ymm6");
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asm volatile("vpaddb %ymm12,%ymm12,%ymm12");
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asm volatile("vpaddb %ymm14,%ymm14,%ymm14");
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asm volatile("vpand %ymm0,%ymm5,%ymm5");
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asm volatile("vpand %ymm0,%ymm7,%ymm7");
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asm volatile("vpand %ymm0,%ymm13,%ymm13");
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asm volatile("vpand %ymm0,%ymm15,%ymm15");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm7,%ymm6,%ymm6");
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asm volatile("vpxor %ymm13,%ymm12,%ymm12");
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asm volatile("vpxor %ymm15,%ymm14,%ymm14");
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asm volatile("vmovdqa %0,%%ymm5" :: "m" (dptr[z][d]));
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asm volatile("vmovdqa %0,%%ymm7"
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:: "m" (dptr[z][d+32]));
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asm volatile("vmovdqa %0,%%ymm13"
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:: "m" (dptr[z][d+64]));
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asm volatile("vmovdqa %0,%%ymm15"
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:: "m" (dptr[z][d+96]));
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asm volatile("vpxor %ymm5,%ymm2,%ymm2");
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asm volatile("vpxor %ymm7,%ymm3,%ymm3");
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asm volatile("vpxor %ymm13,%ymm10,%ymm10");
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asm volatile("vpxor %ymm15,%ymm11,%ymm11");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm7,%ymm6,%ymm6");
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asm volatile("vpxor %ymm13,%ymm12,%ymm12");
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asm volatile("vpxor %ymm15,%ymm14,%ymm14");
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}
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asm volatile("prefetchnta %0" :: "m" (q[d]));
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asm volatile("prefetchnta %0" :: "m" (q[d+64]));
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/* P/Q left side optimization */
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for (z = start-1 ; z >= 0 ; z--) {
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asm volatile("vpxor %ymm5,%ymm5,%ymm5");
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asm volatile("vpxor %ymm7,%ymm7,%ymm7");
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asm volatile("vpxor %ymm13,%ymm13,%ymm13");
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asm volatile("vpxor %ymm15,%ymm15,%ymm15");
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asm volatile("vpcmpgtb %ymm4,%ymm5,%ymm5");
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asm volatile("vpcmpgtb %ymm6,%ymm7,%ymm7");
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asm volatile("vpcmpgtb %ymm12,%ymm13,%ymm13");
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asm volatile("vpcmpgtb %ymm14,%ymm15,%ymm15");
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asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
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asm volatile("vpaddb %ymm6,%ymm6,%ymm6");
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asm volatile("vpaddb %ymm12,%ymm12,%ymm12");
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asm volatile("vpaddb %ymm14,%ymm14,%ymm14");
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asm volatile("vpand %ymm0,%ymm5,%ymm5");
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asm volatile("vpand %ymm0,%ymm7,%ymm7");
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asm volatile("vpand %ymm0,%ymm13,%ymm13");
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asm volatile("vpand %ymm0,%ymm15,%ymm15");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm7,%ymm6,%ymm6");
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asm volatile("vpxor %ymm13,%ymm12,%ymm12");
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asm volatile("vpxor %ymm15,%ymm14,%ymm14");
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}
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asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d]));
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asm volatile("vmovntdq %%ymm3,%0" : "=m" (p[d+32]));
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asm volatile("vmovntdq %%ymm10,%0" : "=m" (p[d+64]));
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asm volatile("vmovntdq %%ymm11,%0" : "=m" (p[d+96]));
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asm volatile("vpxor %0,%%ymm4,%%ymm4" : : "m" (q[d]));
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asm volatile("vpxor %0,%%ymm6,%%ymm6" : : "m" (q[d+32]));
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asm volatile("vpxor %0,%%ymm12,%%ymm12" : : "m" (q[d+64]));
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asm volatile("vpxor %0,%%ymm14,%%ymm14" : : "m" (q[d+96]));
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asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d]));
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asm volatile("vmovntdq %%ymm6,%0" : "=m" (q[d+32]));
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asm volatile("vmovntdq %%ymm12,%0" : "=m" (q[d+64]));
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asm volatile("vmovntdq %%ymm14,%0" : "=m" (q[d+96]));
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_avx2x4 = {
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raid6_avx24_gen_syndrome,
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NULL, /* XOR not yet implemented */
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raid6_avx24_xor_syndrome,
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raid6_have_avx2,
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"avx2x4",
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1 /* Has cache hints */
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