x86/acpi: remove irq-compression trick on 32-bit
We already have a per cpu vector on 32-bit via recent changes, and don't need this trick any more (which trick obfuscates the real GSI mappings and which only triggers on larger systems to begin with): On 3 ioapic system (24 per ioapic) before patch I got: ACPI: PCI Interrupt Link [ILSB] enabled at IRQ 71 IOAPIC[2]: Set routing entry (10-23 -> 0xa9 -> IRQ 64 Mode:1 Active:1) pci 0000:80:01.1: PCI INT A -> Link[ILSB] -> GSI 71 (level, low) -> IRQ 64 ACPI: PCI Interrupt Link [LE5B] enabled at IRQ 67 IOAPIC[2]: Set routing entry (10-19 -> 0xb1 -> IRQ 65 Mode:1 Active:1) pci 0000:83:00.0: PCI INT B -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 65 ACPI: PCI Interrupt Link [LE5A] enabled at IRQ 66 IOAPIC[2]: Set routing entry (10-18 -> 0xb9 -> IRQ 66 Mode:1 Active:1) pci 0000:83:00.1: PCI INT A -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66 ACPI: PCI Interrupt Link [LE5D] enabled at IRQ 65 IOAPIC[2]: Set routing entry (10-17 -> 0xc1 -> IRQ 67 Mode:1 Active:1) pci 0000:84:00.0: PCI INT B -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 67 ACPI: PCI Interrupt Link [LE5C] enabled at IRQ 64 IOAPIC[2]: Set routing entry (10-16 -> 0xc9 -> IRQ 68 Mode:1 Active:1) pci 0000:84:00.1: PCI INT A -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 68 pci 0000:87:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66 pci 0000:87:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 67 pci 0000:88:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 68 pci 0000:88:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 65 pci 0000:8b:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66 pci 0000:8b:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 67 pci 0000:8c:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 68 pci 0000:8c:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 65 after the patch we get: ACPI: PCI Interrupt Link [ILSB] enabled at IRQ 71 IOAPIC[2]: Set routing entry (10-23 -> 0xa9 -> IRQ 71 Mode:1 Active:1) pci 0000:80:01.1: PCI INT A -> Link[ILSB] -> GSI 71 (level, low) -> IRQ 71 ACPI: PCI Interrupt Link [LE5B] enabled at IRQ 67 IOAPIC[2]: Set routing entry (10-19 -> 0xb1 -> IRQ 67 Mode:1 Active:1) pci 0000:83:00.0: PCI INT B -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 67 ACPI: PCI Interrupt Link [LE5A] enabled at IRQ 66 IOAPIC[2]: Set routing entry (10-18 -> 0xb9 -> IRQ 66 Mode:1 Active:1) pci 0000:83:00.1: PCI INT A -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66 ACPI: PCI Interrupt Link [LE5D] enabled at IRQ 65 IOAPIC[2]: Set routing entry (10-17 -> 0xc1 -> IRQ 65 Mode:1 Active:1) pci 0000:84:00.0: PCI INT B -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 65 ACPI: PCI Interrupt Link [LE5C] enabled at IRQ 64 IOAPIC[2]: Set routing entry (10-16 -> 0xc9 -> IRQ 64 Mode:1 Active:1) pci 0000:84:00.1: PCI INT A -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 64 pci 0000:87:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66 pci 0000:87:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 65 pci 0000:88:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 64 pci 0000:88:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 67 pci 0000:8b:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66 pci 0000:8b:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 65 pci 0000:8c:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 64 pci 0000:8c:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 67 As it can be seen that GSIs now get mapped lineary. [ Impact: simplify irq number mapping on bigger 32-bit systems ] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Len Brown <lenb@kernel.org> LKML-Reference: <4A01C35C.7060207@kernel.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>hifive-unleashed-5.1
Yinghai Lu
Ingo Molnar
parent
b2e5d8588d
commit
b9e0353fc8
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@ -1162,22 +1162,9 @@ int mp_register_gsi(struct device *dev, u32 gsi, int triggering, int polarity)
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{
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int ioapic;
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int ioapic_pin;
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#ifdef CONFIG_X86_32
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#define MAX_GSI_NUM 4096
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#define IRQ_COMPRESSION_START 64
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static int pci_irq = IRQ_COMPRESSION_START;
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/*
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* Mapping between Global System Interrupts, which
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* represent all possible interrupts, and IRQs
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* assigned to actual devices.
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*/
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static int gsi_to_irq[MAX_GSI_NUM];
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#else
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if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
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return gsi;
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#endif
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/* Don't set up the ACPI SCI because it's already set up */
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if (acpi_gbl_FADT.sci_interrupt == gsi)
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@ -1196,66 +1183,28 @@ int mp_register_gsi(struct device *dev, u32 gsi, int triggering, int polarity)
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gsi = ioapic_renumber_irq(ioapic, gsi);
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#endif
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/*
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* Avoid pin reprogramming. PRTs typically include entries
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* with redundant pin->gsi mappings (but unique PCI devices);
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* we only program the IOAPIC on the first.
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*/
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if (ioapic_pin > MP_MAX_IOAPIC_PIN) {
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printk(KERN_ERR "Invalid reference to IOAPIC pin "
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"%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
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ioapic_pin);
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return gsi;
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}
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/*
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* Avoid pin reprogramming. PRTs typically include entries
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* with redundant pin->gsi mappings (but unique PCI devices);
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* we only program the IOAPIC on the first.
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*/
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if (test_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed)) {
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pr_debug("Pin %d-%d already programmed\n",
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mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
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#ifdef CONFIG_X86_32
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return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
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#else
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return gsi;
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#endif
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}
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set_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed);
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#ifdef CONFIG_X86_32
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/*
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* For GSI >= 64, use IRQ compression
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*/
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if ((gsi >= IRQ_COMPRESSION_START)
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&& (triggering == ACPI_LEVEL_SENSITIVE)) {
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/*
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* For PCI devices assign IRQs in order, avoiding gaps
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* due to unused I/O APIC pins.
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*/
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int irq = gsi;
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if (gsi < MAX_GSI_NUM) {
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/*
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* Retain the VIA chipset work-around (gsi > 15), but
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* avoid a problem where the 8254 timer (IRQ0) is setup
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* via an override (so it's not on pin 0 of the ioapic),
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* and at the same time, the pin 0 interrupt is a PCI
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* type. The gsi > 15 test could cause these two pins
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* to be shared as IRQ0, and they are not shareable.
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* So test for this condition, and if necessary, avoid
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* the pin collision.
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*/
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gsi = pci_irq++;
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/*
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* Don't assign IRQ used by ACPI SCI
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*/
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if (gsi == acpi_gbl_FADT.sci_interrupt)
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gsi = pci_irq++;
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gsi_to_irq[irq] = gsi;
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} else {
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printk(KERN_ERR "GSI %u is too high\n", gsi);
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return gsi;
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}
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}
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#endif
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io_apic_set_pci_routing(dev, ioapic, ioapic_pin, gsi,
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triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
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polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
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return gsi;
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}
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