MLK-21509-3 drm/imx: dpu: kms: Add auto control mode debugfs CRC support
This patch adds auto control mode debugfs CRC support based on DPU Signature units. The evaluation window is the same to the display region as indicated by drm_crtc_state->adjusted_mode. The CRC data count is three when single DPU display stream is used, while six when the pixel combiner(dual DPU display streams) is used. Each data shows the CRC value for the 8 most significant bits of red/green/blue channel of the entire evaluation window, which reflects how DPU Signature unit reports CRC values. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>5.4-rM2-2.2.x-imx-squashed
Liu Ying
parent
f9d0e0c46f
commit
ba2b101d1f
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@ -1,6 +1,7 @@
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ccflags-y += -I $(srctree)/$(src)/../
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imx-dpu-crtc-objs := dpu-crtc.o dpu-kms.o dpu-plane.o
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imx-dpu-crtc-$(CONFIG_DEBUG_FS) := dpu-crc.o
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obj-$(CONFIG_DRM_IMX_DPU) += imx-dpu-crtc.o
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imx-dpu-render-objs := dpu-blit.o
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@ -0,0 +1,269 @@
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/*
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* Copyright 2019,2020 NXP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <drm/drm_atomic.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_device.h>
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#include <drm/drm_plane.h>
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#include <linux/interrupt.h>
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#include <linux/types.h>
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#include <video/dpu.h>
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#include "dpu-crtc.h"
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static void
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dpu_enable_signature_roi(struct dpu_signature *sig, struct drm_rect *roi)
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{
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signature_continuous_mode(sig, true);
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signature_win(sig, 0, roi->x1, roi->y1, roi->x2, roi->y2);
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signature_eval_win(sig, 0, true);
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signature_shdldreq(sig, 0x1);
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}
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static void dpu_disable_signature(struct dpu_signature *sig)
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{
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signature_continuous_mode(sig, false);
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signature_wait_for_idle(sig);
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signature_eval_win(sig, 0, false);
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}
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static int dpu_crc_parse_source(const char *source_name, enum dpu_crc_source *s)
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{
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if (!source_name) {
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*s = DPU_CRC_SRC_NONE;
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} else if (!strcmp(source_name, "auto")) {
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*s = DPU_CRC_SRC_FRAMEGEN;
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} else {
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return -EINVAL;
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}
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return 0;
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}
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int dpu_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
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size_t *values_cnt)
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{
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struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
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struct imx_crtc_state *imx_crtc_state;
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struct dpu_crtc_state *dcstate;
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enum dpu_crc_source source;
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int ret;
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if (dpu_crc_parse_source(source_name, &source) < 0) {
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dev_dbg(dpu_crtc->dev, "unknown source %s\n", source_name);
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return -EINVAL;
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}
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ret = drm_modeset_lock_single_interruptible(&crtc->mutex);
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if (ret)
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return ret;
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imx_crtc_state = to_imx_crtc_state(crtc->state);
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dcstate = to_dpu_crtc_state(imx_crtc_state);
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*values_cnt = dcstate->use_pc ? 6 : 3;
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drm_modeset_unlock(&crtc->mutex);
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return ret;
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}
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int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name)
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{
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struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
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struct drm_modeset_acquire_ctx ctx;
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struct drm_crtc_state *crtc_state;
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struct drm_atomic_state *state;
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enum dpu_crc_source source;
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int ret;
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if (dpu_crc_parse_source(source_name, &source) < 0) {
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dev_dbg(dpu_crtc->dev, "unknown source %s\n", source_name);
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return -EINVAL;
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}
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/* Perform an atomic commit to set the CRC source. */
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drm_modeset_acquire_init(&ctx, 0);
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state = drm_atomic_state_alloc(crtc->dev);
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if (!state) {
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ret = -ENOMEM;
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goto unlock;
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}
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state->acquire_ctx = &ctx;
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retry:
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crtc_state = drm_atomic_get_crtc_state(state, crtc);
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if (!IS_ERR(crtc_state)) {
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struct imx_crtc_state *imx_crtc_state;
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struct dpu_crtc_state *dcstate;
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imx_crtc_state = to_imx_crtc_state(crtc_state);
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dcstate = to_dpu_crtc_state(imx_crtc_state);
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if ((dcstate->use_pc && crtc->crc.values_cnt != 6) ||
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(!dcstate->use_pc && crtc->crc.values_cnt != 3)) {
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ret = -EINVAL;
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goto put;
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}
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dcstate->crc.source = source;
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dpu_crtc->use_dual_crc = dcstate->use_pc;
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ret = drm_atomic_commit(state);
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} else {
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ret = PTR_ERR(crtc_state);
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}
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if (ret == -EDEADLK) {
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drm_atomic_state_clear(state);
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drm_modeset_backoff(&ctx);
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goto retry;
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}
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put:
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drm_atomic_state_put(state);
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unlock:
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drm_modeset_drop_locks(&ctx);
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drm_modeset_acquire_fini(&ctx);
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return ret;
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}
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irqreturn_t dpu_crc_valid_irq_threaded_handler(int irq, void *dev_id)
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{
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struct dpu_crtc *dpu_crtc = dev_id;
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struct dpu_signature *sig = dpu_crtc->sig;
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struct dpu_crtc *aux_dpu_crtc = dpu_crtc_get_aux_dpu_crtc(dpu_crtc);
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bool dual_crc = dpu_crtc->use_dual_crc;
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unsigned long ret;
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uint32_t crcs[6] = {0, 0, 0, 0, 0, 0};
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dev_dbg(dpu_crtc->dev, "CRC valid irq threaded handler\n");
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signature_crc_value(sig, 0, &dpu_crtc->crc_red,
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&dpu_crtc->crc_green,
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&dpu_crtc->crc_blue);
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if (dual_crc && dpu_crtc->stream_id == 1) {
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complete(&aux_dpu_crtc->aux_crc_done);
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return IRQ_HANDLED;
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}
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crcs[2] = dpu_crtc->crc_red;
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crcs[1] = dpu_crtc->crc_green;
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crcs[0] = dpu_crtc->crc_blue;
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if (dual_crc && dpu_crtc->stream_id == 0) {
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ret = wait_for_completion_timeout(&dpu_crtc->aux_crc_done,
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HZ / 20);
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if (ret == 0)
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dev_warn(dpu_crtc->dev,
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"wait for auxiliary CRC done timeout\n");
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crcs[5] = aux_dpu_crtc->crc_red;
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crcs[4] = aux_dpu_crtc->crc_green;
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crcs[3] = aux_dpu_crtc->crc_blue;
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}
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drm_crtc_add_crc_entry(&dpu_crtc->base, false, 0, crcs);
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return IRQ_HANDLED;
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}
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void dpu_crtc_enable_crc_source(struct drm_crtc *crtc,
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enum dpu_crc_source source)
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{
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struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
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struct dpu_crtc *aux_dpu_crtc = dpu_crtc_get_aux_dpu_crtc(dpu_crtc);
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struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
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struct dpu_crtc_state *dcstate = to_dpu_crtc_state(imx_crtc_state);
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struct drm_display_mode *mode = &crtc->state->adjusted_mode;
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struct completion *shdld_done;
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struct drm_rect roi;
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bool dual_crc = dpu_crtc->use_dual_crc;
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unsigned long ret;
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if (source == DPU_CRC_SRC_NONE)
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return;
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if (dual_crc != dcstate->use_pc)
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return;
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if (dpu_crtc->crc_is_enabled)
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return;
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/* region of interest */
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roi.x1 = 0;
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roi.y1 = 0;
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roi.x2 = dual_crc ? mode->hdisplay >> 1 : mode->hdisplay;
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roi.y2 = mode->vdisplay;
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enable_irq(dpu_crtc->crc_valid_irq);
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enable_irq(dpu_crtc->crc_shdld_irq);
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disengcfg_sig_select(dpu_crtc->dec, DEC_SIG_SEL_FRAMEGEN);
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dpu_enable_signature_roi(dpu_crtc->sig, &roi);
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if (dual_crc) {
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aux_dpu_crtc->use_dual_crc = dual_crc;
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enable_irq(aux_dpu_crtc->crc_valid_irq);
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enable_irq(aux_dpu_crtc->crc_shdld_irq);
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disengcfg_sig_select(dpu_crtc->aux_dec, DEC_SIG_SEL_FRAMEGEN);
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dpu_enable_signature_roi(dpu_crtc->aux_sig, &roi);
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}
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shdld_done = &dpu_crtc->crc_shdld_done;
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ret = wait_for_completion_timeout(shdld_done, HZ);
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if (ret == 0)
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dev_warn(dpu_crtc->dev, "wait for CRC shdld done timeout\n");
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if (dual_crc) {
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shdld_done = &aux_dpu_crtc->crc_shdld_done;
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ret = wait_for_completion_timeout(shdld_done, HZ);
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if (ret == 0)
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dev_warn(dpu_crtc->dev,
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"wait for auxiliary CRC shdld done timeout\n");
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}
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disable_irq(dpu_crtc->crc_shdld_irq);
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if (dual_crc)
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disable_irq(aux_dpu_crtc->crc_shdld_irq);
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dpu_crtc->crc_is_enabled = true;
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dev_dbg(dpu_crtc->dev, "enable CRC source\n");
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}
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void dpu_crtc_disable_crc_source(struct drm_crtc *crtc, bool dual_crc)
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{
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struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
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struct dpu_crtc *aux_dpu_crtc = dpu_crtc_get_aux_dpu_crtc(dpu_crtc);
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if (!dpu_crtc->crc_is_enabled)
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return;
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dpu_disable_signature(dpu_crtc->sig);
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if (dual_crc)
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dpu_disable_signature(dpu_crtc->aux_sig);
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disable_irq(dpu_crtc->crc_valid_irq);
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if (dual_crc) {
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disable_irq(aux_dpu_crtc->crc_valid_irq);
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reinit_completion(&dpu_crtc->aux_crc_done);
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}
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dpu_crtc->crc_is_enabled = false;
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dev_dbg(dpu_crtc->dev, "disable CRC source\n");
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}
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@ -0,0 +1,58 @@
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/*
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* Copyright 2019,2020 NXP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef _DPU_CRC_H_
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#define _DPU_CRC_H_
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#include "dpu-crtc.h"
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static inline bool to_enable_dpu_crc(struct dpu_crtc_state *new_dcstate,
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struct dpu_crtc_state *old_dcstate)
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{
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return old_dcstate->crc.source == DPU_CRC_SRC_NONE &&
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new_dcstate->crc.source != DPU_CRC_SRC_NONE;
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}
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static inline bool to_disable_dpu_crc(struct dpu_crtc_state *new_dcstate,
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struct dpu_crtc_state *old_dcstate)
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{
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return old_dcstate->crc.source != DPU_CRC_SRC_NONE &&
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new_dcstate->crc.source == DPU_CRC_SRC_NONE;
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}
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#ifdef CONFIG_DEBUG_FS
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int dpu_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
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size_t *values_cnt);
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int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
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irqreturn_t dpu_crc_valid_irq_threaded_handler(int irq, void *dev_id);
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void dpu_crtc_enable_crc_source(struct drm_crtc *crtc,
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enum dpu_crc_source source);
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void dpu_crtc_disable_crc_source(struct drm_crtc *crtc, bool dual_crc);
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#else
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#define dpu_crtc_verify_crc_source NULL
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#define dpu_crtc_set_crc_source NULL
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irqreturn_t dpu_crc_valid_irq_threaded_handler(int irq, void *dev_id)
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{
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return IRQ_HANDLED;
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}
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void dpu_crtc_enable_crc_source(struct drm_crtc *crtc,
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enum dpu_crc_source source)
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{
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}
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void dpu_crtc_disable_crc_source(struct drm_crtc *crtc, bool dual_crc)
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{
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}
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#endif
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#endif
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@ -28,6 +28,7 @@
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#include <video/dpu.h>
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#include <video/imx8-pc.h>
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#include <video/imx8-prefetch.h>
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#include "dpu-crc.h"
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#include "dpu-crtc.h"
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#include "dpu-kms.h"
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#include "dpu-plane.h"
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@ -279,6 +280,9 @@ static void dpu_crtc_atomic_enable(struct drm_crtc *crtc,
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crtc->base.id, crtc->name, __func__);
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}
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}
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if (dcstate->crc.source != DPU_CRC_SRC_NONE)
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dpu_crtc_enable_crc_source(crtc, dcstate->crc.source);
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}
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static void dpu_crtc_atomic_disable(struct drm_crtc *crtc,
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@ -296,6 +300,9 @@ static void dpu_crtc_atomic_disable(struct drm_crtc *crtc,
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unsigned long flags;
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int i;
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if (dcstate->crc.source != DPU_CRC_SRC_NONE)
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dpu_crtc_disable_crc_source(crtc, dcstate->use_pc);
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if (dcstate->use_pc) {
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tcon_disable_pc(dpu_crtc->tcon);
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@ -430,6 +437,8 @@ static void dpu_drm_crtc_reset(struct drm_crtc *crtc)
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (state) {
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state->crc.source = DPU_CRC_SRC_NONE;
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crtc->state = &state->imx_crtc_state.base;
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crtc->state->crtc = crtc;
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@ -464,6 +473,7 @@ dpu_drm_crtc_duplicate_state(struct drm_crtc *crtc)
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imx_crtc_state = to_imx_crtc_state(crtc->state);
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state = to_dpu_crtc_state(imx_crtc_state);
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copy->use_pc = state->use_pc;
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copy->crc.source = state->crc.source;
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return ©->imx_crtc_state.base;
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}
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@ -507,6 +517,8 @@ static const struct drm_crtc_funcs dpu_crtc_funcs = {
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.atomic_destroy_state = dpu_drm_crtc_destroy_state,
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.enable_vblank = dpu_enable_vblank,
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.disable_vblank = dpu_disable_vblank,
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.set_crc_source = dpu_crtc_set_crc_source,
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.verify_crc_source = dpu_crtc_verify_crc_source,
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};
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static irqreturn_t dpu_vbl_irq_handler(int irq, void *dev_id)
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@ -555,6 +567,15 @@ static irqreturn_t dpu_dec_shdld_irq_handler(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static irqreturn_t dpu_crc_shdld_irq_handler(int irq, void *dev_id)
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{
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struct dpu_crtc *dpu_crtc = dev_id;
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complete(&dpu_crtc->crc_shdld_done);
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return IRQ_HANDLED;
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}
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static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
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struct drm_crtc_state *crtc_state)
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{
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@ -565,6 +586,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
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struct dpu_plane_state *dpstate;
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struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
|
||||
struct dpu_crtc_state *dcstate = to_dpu_crtc_state(imx_crtc_state);
|
||||
struct imx_crtc_state *old_imx_crtc_state =
|
||||
to_imx_crtc_state(crtc->state);
|
||||
struct dpu_crtc_state *old_dcstate =
|
||||
to_dpu_crtc_state(old_imx_crtc_state);
|
||||
struct drm_display_mode *mode = &crtc_state->adjusted_mode;
|
||||
struct videomode vm;
|
||||
unsigned long encoder_type = DRM_MODE_ENCODER_NONE;
|
||||
|
|
@ -596,6 +621,11 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
|
|||
}
|
||||
}
|
||||
|
||||
/* disallow to enable CRC when CRTC keeps at inactive status */
|
||||
if (!crtc->state->active && !crtc_state->enable &&
|
||||
to_enable_dpu_crc(dcstate, old_dcstate))
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* cache the plane states so that the planes can be disabled in
|
||||
* ->atomic_begin.
|
||||
|
|
@ -743,6 +773,9 @@ static void dpu_crtc_atomic_flush(struct drm_crtc *crtc,
|
|||
if (!crtc->state->active && !old_crtc_state->active)
|
||||
return;
|
||||
|
||||
if (!need_modeset && to_disable_dpu_crc(dcstate, old_dcstate))
|
||||
dpu_crtc_disable_crc_source(crtc, old_dcstate->use_pc);
|
||||
|
||||
/*
|
||||
* Scan over old plane fetchunits to determine if we
|
||||
* need to wait for FrameGen frame counter moving in
|
||||
|
|
@ -923,6 +956,9 @@ again2:
|
|||
extdst_pixengcfg_sync_trigger(ed);
|
||||
}
|
||||
}
|
||||
|
||||
if (!need_modeset && to_enable_dpu_crc(dcstate, old_dcstate))
|
||||
dpu_crtc_enable_crc_source(crtc, dcstate->crc.source);
|
||||
}
|
||||
|
||||
static void dpu_crtc_mode_set_nofb(struct drm_crtc *crtc)
|
||||
|
|
@ -1050,6 +1086,8 @@ static void dpu_crtc_put_resources(struct dpu_crtc *dpu_crtc)
|
|||
dpu_ed_put(dpu_crtc->ed);
|
||||
if (!IS_ERR_OR_NULL(dpu_crtc->fg))
|
||||
dpu_fg_put(dpu_crtc->fg);
|
||||
if (!IS_ERR_OR_NULL(dpu_crtc->sig))
|
||||
dpu_sig_put(dpu_crtc->sig);
|
||||
if (!IS_ERR_OR_NULL(dpu_crtc->tcon))
|
||||
dpu_tcon_put(dpu_crtc->tcon);
|
||||
}
|
||||
|
|
@ -1095,6 +1133,13 @@ static int dpu_crtc_get_resources(struct dpu_crtc *dpu_crtc)
|
|||
}
|
||||
dpu_crtc->aux_fg = dpu_aux_fg_peek(dpu_crtc->fg);
|
||||
|
||||
dpu_crtc->sig = dpu_sig_get(dpu, stream_id);
|
||||
if (IS_ERR(dpu_crtc->sig)) {
|
||||
ret = PTR_ERR(dpu_crtc->sig);
|
||||
goto err_out;
|
||||
}
|
||||
dpu_crtc->aux_sig = dpu_aux_sig_peek(dpu_crtc->sig);
|
||||
|
||||
dpu_crtc->tcon = dpu_tcon_get(dpu, stream_id);
|
||||
if (IS_ERR(dpu_crtc->tcon)) {
|
||||
ret = PTR_ERR(dpu_crtc->tcon);
|
||||
|
|
@ -1152,6 +1197,8 @@ static int dpu_crtc_init(struct dpu_crtc *dpu_crtc,
|
|||
init_completion(&dpu_crtc->safety_shdld_done);
|
||||
init_completion(&dpu_crtc->content_shdld_done);
|
||||
init_completion(&dpu_crtc->dec_shdld_done);
|
||||
init_completion(&dpu_crtc->crc_shdld_done);
|
||||
init_completion(&dpu_crtc->aux_crc_done);
|
||||
|
||||
dpu_crtc->stream_id = stream_id;
|
||||
dpu_crtc->crtc_grp_id = pdata->di_grp_id;
|
||||
|
|
@ -1260,6 +1307,34 @@ static int dpu_crtc_init(struct dpu_crtc *dpu_crtc,
|
|||
}
|
||||
disable_irq(dpu_crtc->dec_shdld_irq);
|
||||
|
||||
dpu_crtc->crc_valid_irq = dpu_map_irq(dpu, stream_id ?
|
||||
IRQ_SIG1_VALID : IRQ_SIG0_VALID);
|
||||
irq_set_status_flags(dpu_crtc->crc_valid_irq, IRQ_DISABLE_UNLAZY);
|
||||
ret = devm_request_threaded_irq(dev, dpu_crtc->crc_valid_irq, NULL,
|
||||
dpu_crc_valid_irq_threaded_handler,
|
||||
IRQF_ONESHOT, "imx_drm", dpu_crtc);
|
||||
if (ret < 0) {
|
||||
dev_err(dev,
|
||||
"CRC valid irq request failed with %d.\n",
|
||||
ret);
|
||||
goto err_put_resources;
|
||||
}
|
||||
disable_irq(dpu_crtc->crc_valid_irq);
|
||||
|
||||
dpu_crtc->crc_shdld_irq = dpu_map_irq(dpu, stream_id ?
|
||||
IRQ_SIG1_SHDLOAD : IRQ_SIG0_SHDLOAD);
|
||||
irq_set_status_flags(dpu_crtc->crc_shdld_irq, IRQ_DISABLE_UNLAZY);
|
||||
ret = devm_request_irq(dev, dpu_crtc->crc_shdld_irq,
|
||||
dpu_crc_shdld_irq_handler, 0, "imx_drm",
|
||||
dpu_crtc);
|
||||
if (ret < 0) {
|
||||
dev_err(dev,
|
||||
"CRC shadow load irq request failed with %d.\n",
|
||||
ret);
|
||||
goto err_put_resources;
|
||||
}
|
||||
disable_irq(dpu_crtc->crc_shdld_irq);
|
||||
|
||||
return 0;
|
||||
|
||||
err_put_resources:
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2017-2019 NXP
|
||||
* Copyright 2017-2020 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
|
|
@ -29,6 +29,7 @@ struct dpu_crtc {
|
|||
struct dpu_disengcfg *dec;
|
||||
struct dpu_extdst *ed;
|
||||
struct dpu_framegen *fg;
|
||||
struct dpu_signature *sig;
|
||||
struct dpu_tcon *tcon;
|
||||
struct dpu_store *st;
|
||||
struct dpu_constframe *aux_pa_cf;
|
||||
|
|
@ -36,6 +37,7 @@ struct dpu_crtc {
|
|||
struct dpu_disengcfg *aux_dec;
|
||||
struct dpu_extdst *aux_ed;
|
||||
struct dpu_framegen *aux_fg;
|
||||
struct dpu_signature *aux_sig;
|
||||
struct dpu_tcon *aux_tcon;
|
||||
/* master */
|
||||
struct dpu_constframe *m_pa_cf;
|
||||
|
|
@ -62,19 +64,34 @@ struct dpu_crtc {
|
|||
int safety_shdld_irq;
|
||||
int content_shdld_irq;
|
||||
int dec_shdld_irq;
|
||||
int crc_valid_irq;
|
||||
int crc_shdld_irq;
|
||||
|
||||
bool aux_is_master;
|
||||
bool use_dual_crc;
|
||||
bool crc_is_enabled;
|
||||
|
||||
struct completion safety_shdld_done;
|
||||
struct completion content_shdld_done;
|
||||
struct completion dec_shdld_done;
|
||||
struct completion crc_shdld_done;
|
||||
struct completion aux_crc_done;
|
||||
|
||||
struct drm_pending_vblank_event *event;
|
||||
|
||||
u32 crc_red;
|
||||
u32 crc_green;
|
||||
u32 crc_blue;
|
||||
};
|
||||
|
||||
struct dpu_crc {
|
||||
enum dpu_crc_source source;
|
||||
};
|
||||
|
||||
struct dpu_crtc_state {
|
||||
struct imx_crtc_state imx_crtc_state;
|
||||
struct dpu_plane_state **dpu_plane_states;
|
||||
struct dpu_crc crc;
|
||||
bool use_pc;
|
||||
};
|
||||
|
||||
|
|
@ -91,4 +108,6 @@ static inline struct dpu_crtc *to_dpu_crtc(struct drm_crtc *crtc)
|
|||
struct dpu_plane_state **
|
||||
crtc_state_get_dpu_plane_states(struct drm_crtc_state *state);
|
||||
|
||||
struct dpu_crtc *dpu_crtc_get_aux_dpu_crtc(struct dpu_crtc *dpu_crtc);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue